ID	原文	译文
43156	首先利用 FBAＲ的一维 Mason 等效电路模型对谐振器进行设计，	The resonator was designed using one dimensional Mason equivalent circuit model firstly.
43157	然后采用实际制作的谐振器模型构成阶梯型结构FBAＲ滤波器，	On the basis of the prepared resonator model, the ladder FBAＲ filter was established.
43158	利用 ADS 软件对 FBAＲ滤波器进行电路原理图以及版图设计优化。	The circuit schematic andlayout of the FBAＲ filter was designed and optimized by ADS software.
43159	仿真结果表明，滤波器的中心频率为 5. 5 GHz，中心插损为 1. 79 dB，1 dB 带宽为 115 MHz，5. 3 GHz 处抑制为 40. 29 dBc，5. 7 GHz 处抑制为 64. 32 dBc。	The simulation results show that the filter center frequency is 5. 5 GHz, the insertion loss at center frequency is 1. 79 dB, the 1 dB bandwidth is 115 MHz, and the rejections at 5. 3 GHz and 5. 7 GHz are 40. 29 dBc and 64. 32 dBc, respectively.
43160	采用空气隙结构实现了 C 波段 FBAＲ滤波器芯片，	The FBAＲ filter chip was realized using air-gap structure.
43161		The ceramic package was used in orderto ensure hermetization.
43162	并采用陶瓷外壳进行气密封装。测试结果显示，滤波器的中心插损为 2. 19 dB，1 dB 带宽为111 MHz，5. 3 GHz 处抑制为 26. 88 dBc，5. 7 GHz 处抑制为 60. 96 dBc。	The measured results show that the filter insertion loss at center frequency is2. 19 dB, the 1 dB bandwidth is 111 MHz, and the rejections at 5. 3 GHz and 5. 7 GHz are 26. 88 dBcand 60. 96 dBc, respectively.
43163	对测试结果与仿真结果的差异进行了分析。	The differences between measured results and simulation results were analyzed.
43164	为了给车载以太网物理层芯片内部的数字电路提供稳定的电源，设计了一种 3. 3 V 转换到 1. 2 V±25 mV 的 DC-DC 降压 ( Buck) 电路。	In order to provide a stable power supply for digital circuits inside automotive Ethernet physical layer chips, a DC-DC Buck circuit which converts a voltage from 3.3 V to 1.2 V±25 mV wasdesigned.The constant on-time control mode was adopted.
43165	电路采用恒定导通时间控制模式，包括片内集成的软启动电路、定时器、过零检测电路和死区时间控制电路。	The circuit includs the on-chip integrated softstartup circuit, timer, zero-crossing detection circuit and dead-time control circuit.