ID	原文	译文
503	采用宽度为2 bit的窗口法实现标量乘运算，减少了标量乘所需的总周期数；通过优化点加倍点操作步骤，提高了乘法器的硬件使用率；使用低计算复杂度的快速模约简实现模乘，提高了整体运算速度。	The scalar multiplication algorithm is implemented by using the window method with 2 bit width toreduce the total cycle numbers of the algorithm significantly. By optimizing the order of operations of pointaddition and point doubling, the hardware utilization rate of multiplier is improved. The module multiplication isrealized by using fast module reduction with low computational complexity, thus the overall operation speed isimproved.
504	为了使模L运算可复用标量乘中的快速模约简，该文提出一种基于Barrett约简的模L算法。	The modular L algorithm based on Barrett reduction is proposed to reuse the fast modular reduction inscalar multiplications.
505	通过优化解压过程中模幂操作过程，精简了步骤并使其可复用模乘。	By optimizing the modular power computation in the decompression process, the steps aresimplified and the modular multiplication can be reused.
506	对所提架构做硬件实现，在TSMC的55 nm CMOS工艺下，面积为746×103等效门，最高频率360 MHz，每秒能够执行公钥生成9.06×104次、签名8.82×104次和验签3.99×104次。	Under the TSMC 55 nm CMOS process, the area of theproposed hardware architecture is 7.46×105 equivalent gate, and the maximum frequency is up to 360 MHz. It canperform 9.06×104 key generations, 8.82×104 signatures and 3.99×104 verifications per second.
507	针对现有图像识别系统大多采用软件实现，无法利用神经网络并行计算能力的问题。	To solve the problem that most existing image recognition systems are implemented in softwarewhich can not utilize the parallel computing power of neural networks.
508	该文提出一套基于FPGA的改进RBF神经网络硬件化图像识别系统，将乘法运算改为加法运算解决了神经网络计算复杂不便于硬件化的问题，并且提出一种基于位比较的排序电路解决了大量数据的快速排序问题，以此为基础开发了多目标图像识别应用系统。	this paper proposes a FPGA imagerecognition system based on improved RBF neural network hardware. The multiplication operation in theneural networks is complex and inconvenient for hardware implementation.
509	系统特征提取部分采用FPGA实现，图像识别部分采用ASIC电路实现。	Furthermore, a sort circuit basedon bit comparison is designed to solve the problem of fast sorting of a large number of data.
510	实验结果表明，该文所提出的改进RBF神经网络算法平均识别时间较LeNet-5, AlexNet和VGG16缩短50%；所开发的硬件系统完成对10000张样本图片识别的时间为165 ms，对比于DSP芯片系统所需426.6 ms，减少了60%左右。	Then, a multi-target image recognition application system is developed. The feature extraction part in the developed system isimplemented by FPGA, and the image recognition part is implemented by ASIC circuit. The experimentalresults show that the average recognition time of the improved RBF neural network algorithm proposed is 50%shorter than that of LeNet-5, AlexNet and VGG16, and the time for the developed hardware system torecognize 10000 sample pictures is 165ms, which is reduced by about 60% compared with 426.6ms required by aDSP chip system.
511	通过分析差分传输管预充电逻辑(DP2L)的电路结构，发现该电路还无法达到完全的功耗恒定特性，仍然存在被功耗攻击的风险。	By analyzing the circuit structure of Differential Pass-transistor Precharge Logic (DP2L), it is foundthat the circuit can not achieve the complete constant power consumption, and there is still a risk of beingattacked by power attack.
512	针对该问题，该文对DP2L的电路结构进行改进，并用Hspice对改进前后的电路进行模拟仿真测试。	To solve this problem, the circuit structure of DP2L is improved by this paper, andthe circuits before and after the improvement are simulated using Hspice.