ID 原文 译文
2203 结合高质量纹理特征，根据纹理特征的光照不变性，设计了一种能有效应对光照突变情况的背景更新模型， We have implemented a background updating model that is based on texture invariance, and can effectively deal with abrupt changes in illumination.
2204 实验结果表明，本文提出的融合纹理特征的前景提取模型不仅能够在光照缓慢变化的情况下有效地对运动目标前景进行提取，而且在光照突变情况下仍然能够进行准确提取， The experimental results show that our proposed method for the extraction of fusion texture features can han-dle both slow changes in light, as well as changes in the foreground due to moving objects. The accuracy of foreground ex-traction can still be improved under the condition of light mutation.
2205 前景提取的准确率相比平均背景模型提高 61.7% ，相比混合高斯模型提高 59.3% 。 Our method performs favorably when judged against the average background model, where, the accuracy of foreground extraction is increased by 61. 7% and 59. 3% compared to the mixed Gaussian model.
2206 ADC/DAC 是计算机技术的重要组成部分之一。 ADC /DAC is one of important parts of computer technology.
2207 本文提出的桥电位架构 ADC，类似于流水线 ADC，也是由多个 StageADC 采用流水线方式构成。 The bridge-potential architecture ADC, simi-lar to the pipeline ADC, is also formed by multiple pipelined type of stageADCs. This paper presents two innovative points:
2208 文中提出了两个创新点:一是桥电位架构，在某个瞬间，基准电位链中必有一个基准电位既对应着模拟输入信号，又对应着数字输出信号，称桥电位， 1.Bridge-potential architecture. At certain moment, there must be a reference potential in the reference potential chain that corresponds to both a digital output signal and an analog input signal, and this reference potential is called the bridge-poten-tial.
2209 相对于流水线 ADC 而言，桥电位 ADC 中的基准电位链扩展了一项功能:将基准电位链中的桥电位直接取出与模拟输入信号相减就等于尾数电压，无需 SDAC; Compared to the pipeline ADC, the reference potential chain in the bridge-potential ADC extended a function by extrac-ting the bridge-potential from the reference potential chain directly and subtracting it from the analog input signal, which is e-qual to the residue voltage and does not need a SDAC.
2210 二是翻转点 ON 式零损开关链，由此构成桥电位提取模块，使得桥电位只需流经仅仅一个零损开关即可被取出。 2.Turning-point ON type zero-loss switch chain. Thus, the bridge po-tential extraction module is constructed, which enables the bridge-potential to go by only one zero-loss switch to be extrac-ted.
2211 这两项改进使得每个 StageADC 都只包含了 SADC，而 SDAC 被摒弃。 With these two improvements, each Stage ADC is enabled to contain SADC only, while SDAC is discarded.
2212 针对卷积神经网络中卷积运算复杂度高而导致计算时间过长的问题，本文提出了一种八级流水线结构的可配置 CNN 协加速器 FPGA 实现方法。 To solve the problem that the time consumption of convolutional neural network is too much, which ismostly caused by the high complexity of convolution operation, an FPGA implementation of a configurable CNN co-acceler-ator with eight-stage pipeline structure is proposed.