ID 原文 译文
53357 本文针对老化引起的时序违规提出了一种抗老化的结构设计 TFM-CBILBO，在一种 BIST 结构——并发内建逻辑块观察器的基础上，复用了其中原本不工作的时序单元， An aging-resilient design called TFM-CBILBO to solve timing violation due to aging is proposed in this paper which is based on a BIST structure—concurrent built-in logic block observer reusing the sequential elements before them idling.
53358 根据电路老化程度切换工作模式，有效防止时序违规的发生。 According to the varieties of aging levels, by change the mode, timing violation can be protected effectively.
53359 在 UMC0. 18μm 工艺下的实验结果表明，TFM-CBILBO 面积开销为 20. 53%~3. 21%，相比非时序拆借方案时延开销降低 40. 0%~71. 6%。 Under UMC0. 18μm process the results of experience demonstrate the area overhead is 20. 53%~3. 21%. Compared with traditional design, the delay overhead saves 40. 0%~71. 6%.
53360 本文设计了高效率的支持两个码率的 CMMB 标准的 LDPC 解码器。 In the paper, A low-power and multi-rate LDPC decoder is designed.
53361 论文采用分层修正最小和算法和存储器压缩技术减少存储器资源的使用;采用备份存储器方法，仅用很少的存储器代价，解决 CMMB 的 LDPC 码存在的存储器读写冲突; The layered min-Sum algorithm and memory compress technology are adopted, which reduces the use of memory resources; Split-memory architecture is proposed to solve the memory conflict problem;
53362 采用硬件资源复用，可以同时处理 1/2 码率和 3/4 码率，减少资源消耗。 Reconfigurable CNU module is designed to support two code rates requirement, rate 1/2 and rate 3/4 which reduces the use of logical resources.
53363 本文设计的 LDPC 解码器，在 SMIC 0. 18m 工艺下进行了综合，综合结果显示，解码器的面积 8. 55mm2，功耗 215. 4mW。 The decoder is synthesized with SMIC 0. 18m process. The results show that the area is 8. 55mm2and power is about 215. 4mW.
53364 随着工艺尺寸的缩减，老化导致的电路不稳定现象越来越严重。 With the shrink of technology to scale, circuit instability caused by aging is becoming an increasingly serious problem.
53365 由于 NBTI 效应造成的老化是渐进的，因此老化是可预测的。 Circuit failure prediction is applicable for overcoming this reliability challenge. It is possible due to the gradual nature of aging degradation.
53366 由此提出了一种具有可配置延迟单元的老化预测电路，并将其中的稳定性校验器和锁存器的功能进行了整合。 In this paper, a novel integrated sensor with configurable delay element for circuit failure prediction is proposed.