ID 原文 译文
53277 芯片采用标准 UMC 0. 18um CMOS工艺，工作电压为 1. 2V 时，消耗电流小于 8mA，后仿真结果表明 2. 4GHz 时，芯片达到 1. 69dB 噪声系数，大于 14. 25dB功率增益以及-1. 1dBm 的输入三阶截点（IIP3）。 The chip uses a standard UMC 0. 18um CMOS process, when working at 1. 2V, the current consumption is less than 8mA, post-simulation result shows that: working at 2. 4GHz, we get 1. 69dB noise figure, larger than 14. 25dB power gain and 1. 1dBm input third-order intercept point (IIP3).
53278 设计满足单芯片阅读器低噪声，低功耗和高线性度的要求。 This design meets the requirements of single-chip reader: low noise, low power consumption and high linearity.
53279 为了解决 CMOS OTA 跨导增益不能线性调节的问题，本文采用 AB 电流镜对 NMOS 和 PMOS 差分对管实现的基本 OTA 进行电流偏置，从而实现了一个跨导增益可以宽幅线性调节的全差分 CMOS OTA 电路。 A CMOS operational trans-conductance amplifier (OTA) which trans-conductance gain can be electronically and linearly tuned is proposed in this paper. The realization method is achieved by biasing the two balanced CMOS OTAs with AB current mirror.
53280 提出的 OTA 能够通过调节外部电流 Iadj 实现线性调节跨导增益，其误差小于 2%，外部电流 Iadj 的调节范围为-40A~40A。 The trans-conductance gain of the proposed OTA can be linearly adjusted through an external bias current, Iadj, for two decades with less than 2% error. The linear adjusting rang of Iadj is from -40A to 40A.
53281 OTA 的差分输入电压摆幅为 200mVp-p，输出电流的非线性度小于 1. 2%。 The input-voltage range of about 200mVp-p with less than 1. 2% nonlinearity is obtained.
53282 电路的性能通过 PSPICE 仿真得到了验证。 The performance of the proposed OTA is discussed and confirmed through PSPICE simulation results.
53283 与基于消息迭代的置信传播译码相比，线性规划（linear programming，LP）译码分析有限长 LDPC 码性能更为有效。 linear programming (LP) decoding is more flexible and effective than message passing iterative decoding in analyzing finite-length LDPC code.
53284 然而，传统 LP 译码算法运算量非常大，不利于系统实现。 However, LP decoding is too complex to implement.
53285 本文结合 LDPC 码校验矩阵的特点，去掉传统LP 译码中不必要的约束，得到一种低复杂度 LP 内点译码算法。 Considering the structure of the parity check matrix of the LDPC codes, this paper proposes a new interior point decoding algorithm with low complexity for LP by removing all of the unnecessary restrictions in traditional LP decoding.
53286 为了降低译码延时，将 LP 内点译码算法与置信传播译码算法结合，提出 LDPC 码混合译码算法。 In order to reduce the decoding latency, a hybrid decoding which combines the interior point decoding and the message passing iterative decoding is presented.