ID 原文 译文
44046 电路由电压基准模块、温度传感器模块、比较器阵列以及误差放大器及其对应的功率管与反馈电阻等组成， The circuit consists of a voltage reference module, a temperaturesensor module, a comparator array, an error amplifier and its corresponding power transistor and feedbackresistors.
44047 通过基准电压与温度传感器输出电压的比较，输出数字控制信号到反馈电阻中的可变电阻模块，改变可变电阻阻值进而改变电路输出电压，实现芯片电压随温度可调。 By comparing the reference voltage with the output voltage of the temperature sensor, a digitalcontrol signal is outputted to the variable resistor module in the feedback resistors.The variable resistanceis used to change the output voltage of the circuit, and finally the chip voltage is adjusted with the temperature.
44048 电路结构简单、易于实现、应用方便，同时电路中引入了修调电阻结构，极大提高了基准输出精度。 The structure of the circuit is simple, easy to realize and convenient to apply, and the trim resistor structure was introduced in the circuit, which greatly improved the output reference accuracy.
44049 电路芯片面积为1.10 mm×0. 64 mm，采用 0. 5 μm CMOS 工艺进行了流片并完成了后期测试验证。 Thechip was fabricated in the 0.5 μm CMOS process with an area of 1.10 mm×0.64 mm and the post-testverification was completed.
44050 结果表明，芯片可实现输出电压的随温度可调，有效解决了 GaN 功率放大器在相同的栅极偏置电压下输出功率随温度升高而减小的问题。 The test results show that the output voltage of the chip can be adjusted withthe temperature, and the problem that the output power of the GaN amplifier decreases with the increaseof the temperature under the same gate bias voltage is solved effectively.
44051 研究了影响垂直双扩散场效应晶体管 ( VDMOS) 器件用 200 mm 硅外延片厚度和电阻率等参数均匀性的关键因素。 The key factors affecting the uniformity of parameters such as thickness and resistivity of 200 mm silicon expitaxial wafers for vertical double-diffused MOS (VDMOS) devices were investigated.
44052 采用 Centura 型常压单片式外延炉，系统研究了生长温度、温度梯度、载气流量以及自掺杂抑制措施对 200 mm 外延层表面质量、厚度、电阻率均匀性的影响机制。 The Centura type atmospher single-wafer epitaxial reactor was used to study the influences mechanism ofthe growth temperature, temperature gradient, carrier gas flow rate and self-doping inhibition measures onthe surface quality, thickness and resistivity uniformity of 200 mm epitaxial layer.
44053 结果表明，在载气总流量为 80 L /min、外延生长温度为 1 125 ℃ 的条件下，通过设计 2 μm的基座浅层包硅厚度，以及高达 6 μm /min 的生长速率等多项自掺杂抑制措施，成功使同一热流场系统内薄层和厚层硅外延片均达到片内厚度不均匀性小于 1. 0%、电阻率不均匀性小于 1. 5%的水平，满足 VDMOS 器件的使用要求。 The results show thatcombined with the H2 carrier gas flow rate of 80 L /min, the epitaxial growth temperature of 1 125 ℃, bydesigning a 2 μm shallow silicon-coated thickness on the susceptor, a growth rate of 6 μm /min, and theoptimized combination of self-doping suppression measures, the thickness non-uniformities of thin-layerand thick-layer silicon epitaxial wafers in the same thermal and flow field system are less than 1.0%, andthe resistivity non-uniformity is less than 1.5%.It can meet the requirements of VDMOS devices.
44054 对硬脆材料氮化镓 ( GaN) 单晶的机械研磨和化学机械抛光 ( CMP) 加工工艺进行了研究。 The mechanical lapping and chemical mechanical polishing (CMP) processing technologies on hard brittle material GaN crystals were investigated.
44055 在机械研磨工艺中，研究了不同材料的研磨盘和不同粒径的磨料对 GaN 研磨时间的影响。 In the process of mechanical lapping, theeffects of lapping plates with different materials and abrasives with different particle sizes were studied.