ID 原文 译文
43886 再将待检片分区与标准片模板进行序贯比对，以提取可疑区域， And then the sample to be inspected was compared with the standard template sequentially to extract the suspicious area.
43887 最后利用支持向量机 ( SVM) 分类器对可疑区域进行筛选分类。 Finally the suspicious region was filtered and classified byusing the support vector machine (SVM) classifier.
43888 实验结果表明，这种方法不仅克服了传统视觉检测过程中视野范围与图像分辨率相互制约的矛盾，且对陶瓷方形扁平封装表面缺陷具有较高的检出率。 The test results show that the proposed method canovercome the contradiction between the visual field range and the image resolution in the traditional visualinspection process, and has a high detection rate for the ceramic quad flat package surface defects.
43889 提出了一种新型隧穿场效应晶体管 ( TFET) 结构， A new structure of tunneling-FET (TFET) was proposed.
43890 该结构通过在常规 TFET 靠近器件栅氧化层一侧的漏－体结界面引入一薄层二氧化硅 ( 隔离区) ，从而减小甚至阻断反向栅压情况下漏端到体端的带带隧穿 ( BTBT) ，减弱 TFET 的双极效应，实现大幅度降低器件泄漏电流的目的。 A thin layer of SiO2 was inserted into the interface of the junction of drain and bulk near the gate-oxide side of the traditional TFET toeliminate or even to block band to band tunneling (BTBT) under a reverse gate bias condition, the bipolar effect of the TFET was decreased, and the leakage current was reduced greatly.
43891 利用 TCAD 仿真工具对基于部分耗尽绝缘体上硅 ( PDSOI) 和全耗尽绝缘体上硅( FDSOI) 的 TFET 和新型 TFET 结构进行了仿真与对比。 The structures of thetraditional TFET and the new TFET based on partially depleted silicon-on-insulator (PDSOI) and fullydepleted silicon-on-insulator (FDSOI) were simulated and compared with TCAD simulation tools.
43892 仿真结果表明，当隔离区宽度为 2 nm，高度大于 10 nm 时，可阻断 PDSOI TFET 的 BTBT，其泄漏电流下降了 4 个数量级; The simulation results show that the BTBT of the PDSOI TFET can be blocked when the isolation region is 2 nmwide and the height is greater than 10 nm, and the leakage current is reduced by 4 orders of magnitude;
43893 而基于 FDSOI的 TFET 无法彻底消除 BTBT 和双极效应，其泄漏电流下降了 2 个数量级。 the BTBT and bipolar effects of the FDSOI TFET cannot be eliminated completely, and the leakage currentis reduced by 2 orders of magnitude.
43894 因此新型结构更适合于 PDSOI TFET。 Therefore, the new structure is more suitable for the PDSOI TFET.
43895 为解决传统过压保护电路功耗大、易受干扰的问题，基于 0. 25 μm CMOS 工艺设计并实现了一种应用于控制器局域网络 ( CAN) 总线芯片的过压保护电路。 An overvoltage protection circuit applied to the controller area network (CAN) bus chip was designed and implemented based on the 0.25 μm CMOS process to solve the problem of high powerconsumption and sensitive to the interference of traditional overvoltage protection circuits.