ID 原文 译文
43826 Ag /Cu2O 薄膜的载流子浓度达到 3. 10×1020 cm－3，比Cu2O 薄膜提高了 2. 38×1020 cm－3。 The carrier concentration of the Ag /Cu2O film was3.10×1020 cm－3, and the concentration of the Ag /Cu2O film was 2.38×1020 cm－3 higher than that of theCu2O film.
43827 XＲD，SEM 和 EDS 结果显示，Ag /Cu2O 薄膜的结晶性比 Cu2O薄膜好，但其粒径有所增大， The results of the XＲD, SEM and EDS show that the crystallinity of the Ag /Cu2O film isbetter than that of the Cu2O film, and the particle size of Ag /Cu2O is increased.
43828 Ag /Cu2O 薄膜中 Ag 元素的原子数分数为 0. 13%。 The atom fraction of Agelement in Ag /Cu2O film is 0.13%.
43829 基于凹槽栅增强型氮化镓高电子迁移率晶体管 (GaN HEMT) 研究了不同的栅槽刻蚀工艺对 GaN 器件性能的影响。 The effects of different gate recess etching processes on performances of E-mode galliumnitride high electron mobility transistors (GaN HEMTs) were studied.
43830 在栅槽刻蚀方面，采用了一种感应耦合等离子体 (ICP) 干法刻蚀技术与高温热氧化湿法刻蚀技术相结合的两步法刻蚀技术，将 AlGaN 势垒层全部刻蚀掉，制备出了阈值电压超过 3 V 的增强型 Al2O3 /AlGaN/GaN MIS-HEMT 器件。 The E-mode Al2O3 /AlGaN/GaNMIS-HEMT devices with a threshold voltage of more than 3 V were fabricated by two-step etching technique, combining inductively coupled plasma (ICP) dry etching technique with high temperature thermaloxidation wet etching technique.The AlGaN barrier layer at the recessed gate were fully etched.
43831 相比于传统的 ICP 干法刻蚀技术，两步法是一种低损伤的自停止刻蚀技术，易于控制且具有高度可重复性，能够获得更高质量的刻蚀界面， Compared with the conventional ICP dry etching technique, the two-step etching was an easy-to-controland highly repeatable etching technique, which could be self-terminated at the AlGaN/GaN interface withnegligible effect on the underlying GaN layer, and a higher quality etching interface could be obtained.
43832 所制备的器件增强型 GaN MIS-HEMT 器件具有阈值电压回滞小、电流开关比(ION /IOFF ) 高、栅极泄漏电流小、击穿电压高等特性。 The fabricated E-mode GaN MIS-HEMT devices by two-step etching technique exhibit the characteristicsof low threshold voltage hysteresis, high ION /IOFF, low gate leakage current and high breakdown voltage.
43833 随着工艺节点减小，对高深宽比接触孔形貌和关键尺寸的精准控制变得愈加困难。 As the process nodes decrease, it becomes more difficult to control the morphology andcritical dimensions of the high aspect ratio contact hole accurately.
43834 基于 40 nm 逻辑器件量产数据，研究了高深宽比接触孔刻蚀工艺参数和刻蚀设备内部耗材的磨损对器件电性能稳定性的影响，并提出了工艺改进方案。 Based on the mass production data ofthe 40 nm logic devices, the influences of etching process parameters of high aspect ratio contact holesand the consumable parts of the etching equipment on the stability of the device electrical parameters werestudied and a process improvement scheme was proposed.
43835 通过减小 SiO2 厚度，减小接触孔深宽比，从而改善孔内聚合物在孔底部沉积的问题; The polymer residue in the bottom of the holeswas improved by reducing the thickness of SiO2 and the aspect ratio of the contact holes.