ID 原文 译文
43776 且薄膜经过高低温循环退火后，XＲD 曲线半高宽和位错密度进一步降低。 Moreover, the full-width-at-half maximum of the XＲD profile and dislocation density of Ge film were reduced after high-low temperature cycle annealing.
43777 通过插入 Si 缓冲层可提高选区外延 Si 基 Ge薄膜的晶体质量，该技术有望应用于 Si 基光电集成。 In conclusion, by using insertingsilicon buffer layer, the crystal quality of selective area epitaxy Ge film on Si can be improved, which will be a promising method for Si-based optoelectronic integration.
43778 负偏压温度不稳定性 (NBTI) 退化是制约纳米级集成电路性能及寿命的主导因素之一， The negative bias temperature instability (NBTI) degradation is one of most important factors restricting the performance and lifetime of nanometer integrated circuits.
43779 基于 40 nm CMOS 工艺对 NBTI 模型、模型提参及可靠性仿真展开研究。 The NBTI model, theextraction of model parameters and the reliability simulation were studied based on 40 nm CMOS process.
43780 首先对不同应力条件下 PMOS 晶体管 NBTI 退化特性进行测试、建模及模型参数提取， Firstly, the NBTI degradation characteristics of PMOS transistors under different stress conditions weretested and modeled, then the parameters for modeling were extracted.
43781 然后建立了基于 NBTI 效应的 VerilogA 等效受控电压源，并嵌入 SpectreTM仿真库中， Then, the VerilogA voltage-controlled voltage source (VCVS) based on NBTI effect was established and embedded into SpectreTM library.
43782 并将此受控电压源引入反相器及环形振荡器模块电路中进行可靠性仿真分析，可有效反映 NBTI 退化对电路性能的影响。 The VCVS was introduced into the circuit, including the inverters and the ring-oscillators, for reliability simulation, which could effectively reflect the influence of the NBTI on the circuit performance degradation.
43783 提出了一套完整可行的电路 NBTI 可靠性预测方法，包括 NBTI 模型、模型参数提取、VerilogA 可靠性模型描述以及电路级可靠性仿真分析， A comprehensive reliability prediction method for NBTI-introduced circuit was proposed, which involved NBTI modeling, extraction of parameters for model, VerilogA reliability model and circuit levelreliability simulation.
43784 可为纳米级高性能、高可靠性集成电路设计提供有效参考。 It can provide an valuable guide for the design of high performance and high reliability nanometer integrated circuits.
43785 超大规模集成电路后道工艺 (BEOL) 中的失效日益增多，例如多层金属化布线桥连、划伤，栅氧化层的静电放电 (ESD) 损伤、裂纹等失效模式， Failures in the back end of line (BEOL) of very large scale integration (VLSI) have become more and more, such as the multilayered metallization bridge /scratch defect, gate oxide layer electrostatic discharge (ESD) damage and rupture defect.