ID 原文 译文
43656 实验结果为高性能 CSAC 的研究提供了参考。 Theexperimental results provide a reference for the research of high performance CSAC.
43657 基于 HHNEC 0. 35 μm 40 V BCD 工艺，采用峰值电流检测模式的脉冲宽度调制方式，设计了一款能在 8～42 V 的输入电压范围内，－40 ～ 125 ℃ 的温度范围内正常工作的高转换效率、高输出电流精度的发光二极管 ( LED) 驱动电路，版图面积为 925. 3 μm×826. 8 μm。 A light emitting diode (LED) driver circuit with high conversion efficiency and highoutput current precision was designed based on HHNEC 0.35 μm 40 V BCD process and pulse widthmodulation of peak current detection mode.The LED driver circuit can work normally with an inputvoltage range of 8 － 42 V in the temperature range of － 40 － 125 ℃ .The layout area is 925.3 μm ×826.8 μm.
43658 利用带负反馈的预稳压电路为基准源电路和线性稳压器提供稳定的工作电压， The prestabilized circuit with negative feedback was used to provide stable operating voltagefor reference source circuit and linear regulator.
43659 新颖求和型 CMOS 基准电流源提供低温漂、高精度的偏置电流， The novel summation CMOS reference current source wasuse to provide the bias current with low temperature drift and high precision.
43660 带预抑制电路的基准电压源提供高精度的参考电压，提高了输出电流的精度。 And the reference voltage source with pre-suppression circuit was use to provide the reference voltage with high precision which improves the accuracy of the output current.
43661 仿真结果表明，在典型工艺角 TT 下，当输入电压为 40 V，驱动 9 个 LED，输出电流为 400 mA 时，该 LED 驱动电路转换效率为 95. 8%，输出电流精度为 1. 75%。 The simulation results show that the conversion efficiency of theLED driver circuit is 95.8%, and the output current precision is 1.75% under the typical TT processcorner, when the input voltage is 40 V, driving 9 LEDs, and the output current is 400 mA.
43662 设计了一种适用于 1. 0～ 2. 0 GHz 的高线性下变频混频器。 A high linearity down-conversion mixer operating from 1.0 to 2.0 GHz was designed.
43663 电路设计采用了无源双平衡结构，片内集成宽带巴伦、限幅本振放大器、混频核和偏置电路。 The passive double balanced mixer consists of a wideband balun, a limiting local oscillator (LO) amplifier, a mixer core and bias circuits.
43664 为了提高混频器的线性度，在对无源双平衡的结构进行分析的基础上，折中选择混频核的晶体管尺寸，并优化了本振放大器输出信号的幅值及上升时间。 To improve the linearity of the mixer, based on the analysis of thepassive double balanced mixer, the size of the transistor in the mixer core was compromised, the amplitude and rising time of the output signal of the LO amplifier was optimized.
43665 基于 0. 35 μm BiCMOS 工艺进行了设计仿真，芯片面积为 0. 9 mm×1. 8 mm。 The circuit was designed andsimulated based on the 0.35 μm BiCMOS process and the chip size is 0.9 mm×1.8 mm.