ID 原文 译文
43556 设计采用传统三阶级联反馈型( CＲFB) 结构，并基于图形处理器单元 ( GPU) 加速的连续时间 Δ-Σ ADC 调制器系数设计方法针对系统系数进行了优化。 The traditional 3-stage-cascade resonator feedback (CＲFB) construction was adopted, and the system coefficients were optimized based on the graphics processing unit (GPU) -accelerated continuoustime Δ-Σ ADC modulator coefficient design method.
43557 设计在 3 组可调电阻、电容阵列的基础上针对反馈电流数模转换器( DAC) 以及运算放大器进行了功耗可调设计，从而实现了功耗、输入带宽的高度可调特性。 Three adjustable resistance arrays and capacitor arrays were designed while both the feedback current digital-to-analog converter (DAC) and operational amplifiers were designed with several power-performance flexible modes to realize the highly flexibility inboth power consumption and input bandwidth.
43558 仿真结果表明，Δ-Σ ADC 在30 MHz带宽模式下能够实现 81. 36 dBc 的无杂散动态范围 ( SFDＲ) ，在 1 ～ 32 MHz 的不同带宽模式下能够实现 80 ～ 85. 9 dB 的信噪失真比 ( SNDＲ) 。 The simulation results show that the Δ-Σ ADC achieves81.36 dBc spurious-free dynamic range (SFDＲ) in 30 MHz bandwidth mode and 80－85.9 dB signal-tonoise and distortion ratio (SNDＲ) across all the modes.
43559 整个接收系统的测试结果表明，在保证系统整体性能的情况下，在 1，5，10，20 和 32 MHz 带宽模式下其功耗分别为 33. 7，45，48. 9，77. 1 和 101 mW。 According to the measurement results of thewhole receiver system, the Δ-Σ ADC consumes 33.7, 45, 48.9, 77.1 and 101 mW in 1, 5, 10, 20and 32 MHz mode, respectively, while keeping the performance of the system.
43560 Δ-Σ ADC 的芯片面积为 0. 55 mm2。 The chip of the Δ-Σ ADCoccupies an area of 0.55 mm2.
43561 介绍了一种应用在 DC-DC 变换器芯片中的片内电源电路。 An on-chip power supply circuit applied in DC-DC converters was designed.
43562 其核心是设计了一种带“浮地”结构的对称型跨导放大器电路，既可显著提高电路的瞬态响应速度，也减少了硬件成本，且电路结构简单、易于实现。 The core ofthe circuit was to design a symmetrical transconductance amplifier circuit with " floating ground "structure.The transient response speed of the circuit was significantly increased, while the hardware costwas reduced.And the circuit was simple and easy to be implemented.
43563 此外，设计了一种片外电源检测电路，当存在片外 5 V 电源时，将其接入 DC-DC 变换器中作为片内主电源， In addition, an off-chip power supply detection circuit was designed, which could be connected to the DC-DC converter as the on-chip mainpower supply when the off-chip power supply was 5 V.
43564 提高了芯片效率。 As the main power supply in the chip, the chip efficiency can be improved better.
43565 该片内电源电路已在基于0.5 μm双极-CMOS-DMOS ( BCD) 工艺设计的 DC-DC 变换器中实现了验证， The on-chip power supply circuit was verified in a DC-DC converterbased on 0.5 μm bipolar-CMOS-DMOS (BCD) process.