ID 原文 译文
43546 测试结果表明，该 DAC 在 0. 1 ～ 10 MHz 的信号带宽下，具有63. 0～76. 8 dB 的信噪失真比 ( SNDＲ) 和 67. 9～ 77. 9 dB 的无杂散动态范围 ( SFDＲ) ; The test results show that it achieves a signal-to-noise and distortion ratio(SNDＲ) of 63.0－76.8 dB and spurious-free dynamic range (SFDＲ) of 67.9－77.9 dB in a 0.1－10 MHzsignal bandwidth.
43547 在 1. 5 V的供电电压下的最大功耗为 2. 2 mW。 The maximum power dissipation of the DAC is less than 2.2 mW under 1.5 V power supply.
43548 基于开关电容分割结构设计并实现了一种分辨率为 6 ～ 10 bit 可配置的逐次逼近寄存器型 ( SAＲ) 模数转换器 ( ADC) 。 A successive approximation register (SAＲ) analog-to-digital converter (ADC) with aresolution reconfigurable of 6－10 bit was designed and implemented, based on switching capacitor splitting structure.
43549 对这种电容分割结构的功耗性能、静态非线性以及电源噪声抑制模型等进行了详细分析，并与其他开关电容结构进行了比较。 The power performance, static nonlinear and power noise suppression model of thecapacitor splitting structure were analyzed in detail, and compared to other switched capacitor structures.
43550 采用 0. 18 μm CMOS 工艺完成了分辨率可配置 SAＲ ADC 的流片，其核心部分芯片面积仅为 360 μm× 550 μm。 Using a standard 0.18 μm CMOS process, the resolution reconfigurable SAＲ ADC were implementedwith a core chip area of only 360 μm× 550 μm.
43551 测试结果表明，该 ADC 覆盖了 6～10 bit 分辨率，电源电压为 0. 5 ～ 0. 9 V。 The test results show that the resolution and power supplyvoltage of the SAＲ ADC are 6－10 bit and 0.5－0.9 V, respectively.
43552 在 6，8 和 10 bit 分辨率模式下，该ADC 的功耗分别为 10. 8，16. 1 和 22. 4 μW， At 6, 8 and 10 bit resolution mode, the power of the proposed SAＲ ADC is 10.8, 16.1 and 22.4 μW, respectively.
43553 微分非线性误差为 0. 16 最低有效位 ( LSB) 、积分非线性误差只有 0. 1 LSB。 The differential nonlinearity error is 0.16 least significant bit (LSB) and the integral non-linearity error is only 0.1 LSB.
43554 该 ADC 实现了分辨率、电源电压等参数的可配置。 There configurabilities of resolution, power supply voltage and other parameters of the ADC are realized.
43555 提出了一种带宽为 1 ～ 32 MHz、以 1 MHz 为步进的可调的连续时间 Δ-Σ 模数转换器( ADC) ，并且在标准 65 nm CMOS 工艺下进行了流片验证。 A continuous-time Δ-Σ analog-to-digital converter (ADC) with adjustable bandwidthfrom 1 MHz to 32 MHz stepping 1 MHz was proposed and implemented in a standard 65 nm CMOSprocess.