ID 原文 译文
43536 通过改变测试脉冲上升或下降时间，分析了三维器件界面缺陷能级分布，得出缺陷能级呈现类似 “U”型分布。 The defect level distributions of three-dimensional devices wereanalyzed by changing the rise and fall time of the pulse.And it is found that the defect level exhibits asimilar U-type distribution.
43537 通过在源、漏区施加不同电压，对缺陷沿沟道水平分布进行研究，得到界面缺陷在靠近源、漏区的量最大而在远离源、漏区的位置无规则分布。 Then the horizontal distributions along the channel of defects were studied by changing voltages at source and drain regions.It is concluded that defects have the largest amount close tothe source or drain regions and irregular distribution at locations away from the regions.
43538 通过改变脉冲保持时间，对缺陷沿高介电常数叠栅垂直分布进行研究，可以明显区分开缺陷在中间介质层和高介电常数层的缺陷量。 The study of thevertical distributions of defects was studied along the high dielectric constant stacked gate by changing thehold time of the pulse to clearly distinguish the defect amount in the middle dielectric layer and the highdielectric constant layer.
43539 另外，利用电荷泵技术验证了三维器件负偏压温度不稳定性 ( NBTI) 与界面缺陷的关系。 In addition, the relationships between negative bias temperature instability (NBTI) of 3D devices and interface defects were also evaluated by charge pumping technology.
43540 设计了一款应用于 GSM/WCDMA/LTE 发射机中的多模 10 bit 数模转换器 ( DAC) ， A multi-mode 10 bit digital-to-analog converter (DAC) for GSM/WCDMA/LTE transmitter was designed.
43541 该DAC 采用了 5+5 的分段式电阻型结构，达到面积和性能优化折中。 The DAC adopted a 5+5 segmented resistive architecture to achieve a good trade-offbetween the area and performance.
43542 通过数字可编程设计，该DAC 可根据不同带宽和数据率的要求合理地控制偏置电流的大小，实现不同应用场景的低功耗目标。 In order to reduce the power consumption of the DAC in different application scenarios, the bias current of the DAC can be reasonably controlled by digital programming, according to different signal bandwidths and data rates.
43543 此外，该 DAC 还集成了一款改进的直流偏移自校准电路，将发射机本振泄露的抑制提高了 20 dB 以上。 Moreover, by integrating an improved DC-offset selfcalibration circuit, the DAC improves the local oscillation leakage suppression of the transmitter by morethan 20 dB.
43544 而且，直流偏移自校准在芯片上电期间完成，既不影响通道的正常工作，又不消耗额外的功耗，解决了现有的技术问题。 The DC-offset self-calibration was done during the power-on sequence of the chip, which didn＇taffect the normal work of the channel and didn＇t consume any additional power, solving the problems of theexisting techniques.
43545 该 DAC 采用 0. 13 μm 1P4M CMOS 工艺进行设计和流片，占用芯片面积小于 0. 1 mm2。 The DAC was designed and implemented in a 0.13 μm 1P4M CMOS process with anarea of less than 0.1 mm2.