ID 原文 译文
43416 指出在微米 AlN 粉体制备方面，碳热还原法和直接氮化法仍具有明显优势，而化学气相沉积法和等离子体法则在纳米 AlN 粉体制备方面具有良好的应用前景。 It is pointed out that the carbothermal reductionmethod and the direct nitridation method still have obvious advantages in the preparation of micron-sizedAlN powder, while the chemical vapor deposition method and the plasma method have good applicationprospects in the preparation of nano-sized AlN powder.
43417 获得更高纯度、粒度可控、形貌均匀分散的粉体是 AlN 制备技术的研究方向。 The research direction of the AlN preparationtechnology is to obtain powders with higher purity, controllable particle size and uniformly dispersed morphology.
43418 设计了一种基于改进共源共栅电流镜的 CMOS 电流比较器，该比较器在 1 V 电压且电压误差±10%的状态下都正常工作，同时改进后的结构能够在低电压下取得较低的比较延迟。 A CMOS current comparator based on an improved cascode current mirror was designed.The comparator works normally at 1 V voltage with a voltage error of ±10%, and the improved structurecan achieve lower comparative delay at low voltage.
43419 电路的输入级将输入的电流信号转化为电压信号，电平移位级的引入使该结构能够正常工作在不同的工艺角和温度下，然后通过放大器和反相器得到轨对轨输出电压。 The input stage of the circuit converts the input current signal into the voltage signal.The introduction of the level shift stage enables the circuit to work normally at different process corners and temperatures.
43420 基于 SMIC 0. 18 μm CMOS工艺进行了版图设计， Then, the rail-to-rail output voltage was obtainedthrough amplifiers and inverters.
43421 并使用 SPECTＲE 软件在不同工艺角、温度和电源电压下对电路进行了仿真。 Finally, the layout was designed based on SMIC 0.18 μm CMOS processand the circuit was simulated by SPECTＲE software at different process corners, temperatures and powersupply voltages.
43422 结果表明，该电路在 TT 工艺角下的比较精度为 100 nA，平均功耗为 85. 53 μW，延迟为2. 55 ns， The results show that the circuit achieves a comparative accuracy of 100 nA at TT processcorner with an average power consumption of 85.53 μW and a delay of 2.55 ns.
43423 适合应用于高精度、低功耗电流型集成电路中。 So, it is suitable for the high accuracy low power consumption current-mode integrated circuit.
43424 在不调整制备工艺、不增加工艺成本条件下，研究了管芯版图优化对功率 n 型横向扩散金属氧化物半导体 ( NLDMOS) 电学安全工作区 ( E-SOA) 的影响。 The effects of layout optimization on the electrical safe operating area (E-SOA) of thepower n-type laterally diffused metal oxide semiconductor (NLDMOS) were studied without adjusting fabrication process and increasing process cost.
43425 通过研究 p+带嵌入方式、p+图形形状、p+分布密度、阵列单元栅宽及总栅数、金属引线方式等进行了版图设计优化和流片。 The layout design optimization and chip fabrication were carried out by studying the p+ band embedding ways, p+ pattern shapes, p+ distribution densities, array cellgate width and total gate numbers, metal lead ways and so on.