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43086 通过对不同版图布局的MOS 器件饱和电流进行分析，研究了 130 nm CMOS 工艺中浅槽隔离 ( STI) 和金属硅化物引起的应力对器件饱和电流的影响。 Based on the analysis of the saturation current ofMOS devices with different layouts, the influence of the stress induced by shallow trench isolation (STI)and silicide on the saturation current of MOS devices in 130 nm CMOS process was studied.
43087 结果表明，器件沟道长度方向的 STI 应力使 PMOS 器件饱和电流提高 10%左右，同时使 NMOS 器件饱和电流降低 20% ～30%; The results show that STI stress in the channel length direction increases the saturation current of PMOS devices byabout 10%, meanwhile, it reduces the saturation current of NMOS devices by 20% ～ 30%.
43088 而沟道宽度方向 STI 应力使 NMOS 器件饱和电流降低 16% ～20%，使 PMOS 器件饱和电流降低 14%。 STI stress inchannel width direction reduces the saturation currents of NMOS devices and PMOS devices by 16% ～20% and 14%, respectively.
43089 相对来说，除了沟道长度方向的金属硅化物拉伸应力对 NMOS 器件影响较大外，金属硅化物引起的其他应力对 MOS 器件性能的影响较弱。 Ｒelatively, except the obvious impact on NMOS device performance from the silicide-induced tensile stress along the channel length direction, other stresses induced by silicide has a weakinfluence on the performance of MOS devices.
43090 通过对 130 nm CMOS 工艺应力的分析，可以指导版图设计，从而改善器件和电路性能。 Through the analysis of the stress in 130 nm CMOS process, the device layout design can be guided and the device and circuit performance can be improved.
43091 Ⅲ-Ⅴ/Si 混合集成的反馈外腔半导体光源及其相关集成器件成为近年来的研究热点， Ⅲ-Ⅴ/Si hybrid integrated feedback external cavity semiconductor light source andrelated integrated devices have become research hotspots in recent years.
43092 大容差范围是该类器件提高成品率和降低制备成本的有效途径。 The large tolerance range is aneffective way to improve the yield and reduce the manufacturing cost of the devices.
43093 采用有限差分光束传播法，针对应用于大尺寸Ⅲ-Ⅴ/Si 混合集成波导的双锥形耦合器结构进行了仿真，研究了实现高效耦合结构参数容差范围。 The finite-differencebeam propagation method was used to simulate the dual taper coupler structure applied to the large-sizeⅢ-Ⅴ/Si hybrid integrated waveguide, and the tolerance range of the high-efficiency coupling structureparameter was studied.
43094 结果表明，当Ⅲ-Ⅴ材料有源波导中缓冲层厚度为 0. 5～0. 7 μm，有源波导锥形区长度为 400 ～ 800 μm，锥形区尖部宽度为 0. 5 ～ 0. 55 μm，有源波导增益区宽度为 2. 9 ～ 3. 1 μm，无源波导锥形区的长度超过 500 μm，有源波导相对于 Si 波导的偏移量小于 1 μm 时，Ⅲ-Ⅴ/Si混合集成波导的耦合效率均可达到 90%以上。 The results show that the coupling efficiency of the Ⅲ-Ⅴ/Si hybrid integratedwaveguide can be achieved at least 90% when the thickness of the buffer layer in the Ⅲ-Ⅴ materials active waveguide is 0.5－0.7 μm, the length of the active waveguide cone is 400－800 μm, the width of thetapered tip is 0.5－0.55 μm, the width of the waveguide gain region is 2.9－3.1 μm, the length of thetapered portion of the passive waveguide exceeds 500 μm, and the offset of the active waveguide relativeto the Si waveguide is less than 1 μm.
43095 研究双锥形Ⅲ-Ⅴ/Si 波导高效耦合参数的容差范围可为下一步制备出高效耦合的该类大尺寸混合集成器件提供参考。 The tolerance range study of the high efficiency coupling parameters of the dual taper Ⅲ-Ⅴ/Si waveguide can provide a reference for the preparation of such large-scalehybrid integrated devices with high efficiency coupling.