ID 原文 译文
43066 对电源输出波形异常原因进行分析，电源限流过小导致电源电压降低，从而造成加电时快速突跳。 The abnormal reason of the poweroutput waveform was analyzed, the fast hop of the supply power when power-on was caused by the decreaseof the voltage that was resulted from unreasonable current limit.
43067 最后，搭建测试电路对功率运算放大器进行复现实验，进一步证明了器件的失效机理。 Finally, the repetition test was appliedbased on the test circuit, the failure mechanism of the power operational amplifier was further proved.
43068 提出了一种高能效的细粒度可重构的深度神经网络 ( DNN) 加速芯片。 A highly energy-efficient fine-grained reconfigurable deep neural network (DNN) accelerating chip was proposed.
43069 该芯片是基于并行计算阵列设计的， This chip was designed based on the parallel computing array.
43070 它包含 144 个处理单元，多个处理单元可以实现卷积、矩阵乘、取最大值或取平均值等运算，可以用于加速 DNN。 It consisted of144 processing elements.Multiple processing elements can perform convolution, matrix multiplication, maximum pooling or average pooling, etc., which can be used to accelerate DNN.
43071 每个处理单元之间是通过片上网络 ( NOC) 连接的， Each processing element was connected through the network on chip (NOC) .
43072 每个处理单元的运算结果可以直接发送给相邻的处理单元，运算中间数据不需要缓存。 The results of each processing element can besent directly to the adjacent processing element, and there was no need to cache intermediate data.
43073 相邻处理单元间的数据流可以自由配置成各种拓扑结构，从而适配运算的多样性。 The adjacent processing elements can be freely combined into a variety of topological structures, thusadapting to the diversity of operations.
43074 为了实现激活函数，提出了一种高效的映射非线性函数的硬件实现方法。 In order to realize the activating function, an efficient hardware implementation method for mapping the non-linear function was proposed.
43075 该芯片采用了标准的 130 nm CMOS 工艺制造，芯片面积为 5. 77 mm2。 This chip was fabricated bystandard 130 nm CMOS process with chip area of 5.77 mm2.