ID 原文 译文
42986 该方法可提高 HTＲB 测试效率和准确性。 This method can improve the efficiency and accuracy of the HTＲB test.
42987 新型纳米器件被视为摩尔定律极限临近情况下 CMOS 技术的有力补充。 New nanodevices are considered to be a significant complement to CMOS techniques atthe end of Moore＇s Law.
42988 为克服新型纳米器件缺陷率高的问题，提出了一种基于现场可编程纳米线互连 ( FPNI) 架构的具有自修正能力的纠错 ( FT) 专用集成电路 ( ASIC) 架构 FT-FPNI，这种架构适用于易出错的纳米器件逻辑门电路。 To overcome the problem of high defect rate of new nanodevices, a field-programmable nanowire interconnect (FPNI) architecture based fault-tolerant (FT) application-specific integrated circuit (ASIC) architecture FT-FPNI with self-repair capability was proposed, which wassuitable for fault-prone nanodevice logic gate circuits.
42989 使用基于硬件描述语言的缺陷注入技术来仿真架构，仿真结果表明，这种架构可以100%检测缺陷和错误。 Hardware description language based fault injectiontechnique was used to simulate the architecture.Simulation results show that the proposed architecturecan detect defects and faults at the rate of 100%.
42990 为取得最小的纠错代价，需要保持尽可能小的单元阵列尺寸。 To achieve the lowest fault-tolerant cost, the unit arraysize should be as small as possible.
42991 Hspice 软件仿真结果表明，碳纳米管或非 ( NOＲ) 门输出延迟为 2. 89 ps，平均功耗为 6. 748 pW， The Hspice software simulation results show that the output delay andthe average power consumption of the carbon nanotube field effect transistor NOＲ gate is 2.89 ps and6.748 pW, respectively.
42992 与现有CMOS 技术相比功耗降低 2 个数量级。 Compared with the existing CMOS technique, the power consumption isreduced by two orders of magnitude.
42993 基于 180 nm 绝缘体上硅 ( SOI) CMOS 工艺，设计了一款大功率、低插入损耗的单刀双掷 ( SPDT) 反射式射频开关。 Based on the 180 nm silicon-on-insulator (SOI) CMOS process, a single-pole doublethrow (SPDT) reflective ＲF switch with high power and low insertion loss was designed.
42994 提出了一种体区自适应偏置技术，无需偏置电阻对开关管体区进行偏置。 A body selfadapting bias technique was proposed to remove the bias resistor at the body of the switch FET.
42995 采用并联电容补偿技术优化最大输入功率， The shuntcapacitor compensation technology was applied to optimize the maximum input power.