ID 原文 译文
42946 同时应用低温外延技术、无 HCl 抛光技术， And by usingthe technology of low temperature epitaxy and HCl-free polishing, the ultra-high-resistance thin-layer silicon epitaxial wafer was successfully developed.
42947 研制出超高阻薄层硅外延片，外延层电阻率为 1 093 Ω·cm，外延层厚度为 12. 06 μm，满足外延层厚度 ( 12±1) μm、外延层电阻率大于 1 000 Ω·cm 的设计要求， The thinkness of the epitaxial layer is 12.06 μm, the resistivity of the epitaxial layer is 1 093 Ω·cm, which satisfies the design requirements of the epitaxiallayer thickness (12±1) μm and epitaxial layer resistivity over 1 000 Ω·cm.
42948 片内电阻率不均匀性为 4. 36%，片内厚度不均匀性为 0. 5%。 The resistivity nonuniformity across the wafer is 4.36%, and the thickness nonuniformity across the wafer is 0.5%.
42949 外延片已用于批量生产。 The epitaxialwafers have been used in batch production.
42950 基于 GSMC 130 nm 工艺设计并制备了一款 4 通道垂直腔面发射激光器 ( VCSEL) 阵列驱动电路芯片。 A 4-channel vertical cavity surface emitting laser (VCSEL) array driver circuit chip wasdesigned and fabricated based on GSMC 130 nm process.
42951 该芯片核心电路主要包括限幅放大器 ( LA) 、输出级驱动电路、带隙基准电压源、8 bit 数模转换器 ( DAC) 电路等。 The core circuit of the chip mainly includes alimiting amplifier (LA) , an output stage driving circuit, a bandgap reference voltage source and an 8 bitdigital-to-analog converter (DAC) circuit, etc.
42952 输出级驱动电路将 LA 输出的电压信号转换成电流信号，并配合偏置电路驱动 VCSEL，实现调制发光， The output stage driver circuit converted the voltagesignal output by the LA into a current signal and driving VCSEL to achieve modulated illumination with the bias circuit.
42953 其中 LA 采用有源电感峰化结构，其峰化强度可通过 DAC 进行配置，输出级驱动加入前馈电容补偿技术以拓展带宽。 The LA adopted an active inductor peaking structure, and its peaking intensity could beconfigured by the DAC.The output stage driver was added with the feedforward capacitance compensation technology to expand the bandwidth.
42954 在典型输出配置 ( 输入差分峰峰值 200 mV、5 Gbit /s 的 PＲBS7 信号) 下，每个通道可输出最大 12. 5 mA 的调制电流和 2 mA的偏置电流。 In a typical output configuration (input differential peak-to-peakvalue of 200 mV, 5 Gbit /s PＲBS7 signal) , each channel can output a maximum modulation current of12.5 mA and a bias current of 2 mA.
42955 芯片实测结果表明，在典型输出配置下得到干净清晰的 5 Gbit /s 眼图，每个通道的总抖动为 31. 535 ps，功耗为 84. 5 mW。 The measured results of the chip indicate that in the typical outputconfiguration, the eye diagram is clean and clear, the total jitter of each channel at 5 Gbit /s is 31.535 ps, and the power consumption of each channel is 84.5 mW.