ID 原文 译文
42786 采用 TSMC 55 nm CMOS 工艺进行了流片验证。 The DAC was fabricated and verified in TSMC 55 nm CMOS process.
42787 测试结果表明，2. 5 GS / s采样速率下、输出信号频率 1. 000 9 GHz 时，该 DAC 的无杂散动态范围为 62. 21 dBc，噪声功率谱密度约为－154 dBm/Hz，功耗约为 226 mW，芯片面积为2.5 mm×1. 8 mm。 The test results show that the DAC has a spurious free dynamic range of 62.21 dBc, a noise power spectral densityof about － 154 dBm /Hz, a power consumption of about 226 mW at 2.5 GS / s sampling rate and1.000 9 GHz output signal frequency.The chip area is 2.5 mm×1.8 mm.
42788 化学机械平坦化 ( CMP) 过程中极易在铜表面产生碟形坑、腐蚀坑等缺陷。 In the process of chemical mechanical planarization (CMP) , the defects, such asdishing pits and erosion pits are easily generated on the Cu surface.
42789 为了解决这些问题，提出了将苯并异噻唑啉酮 ( BIT) 作为 CMP 抛光液中的表面抑制剂，研究不同质量分数的 BIT 在 Cu CMP 过程对 Cu 的去除速率、SiO2 介质对 Cu 的选择性及抛光后表面形貌的影响。 In order to solve these problems, thebenzoisothiazolinone (BIT) used as a surface inhibitor in the CMP polishing slurry was proposed.Duringthe Cu CMP process, the effects of the BIT with different mass fraction on the removal rate of Cu, the selectivity of SiO2 to Cu and the surface morphology after polishing were studied.
42790 研究结果表明，随着 BIT 质量分数的增加，SiO2 的去除速率基本不变，Cu 的去除速率由31.6 nm·min－1降到 21. 0 nm·min－1，碟形坑深度由 110 nm 降到 40 nm，腐蚀坑深度由 85 nm 降到 35 nm。 The study results show thatwith the increase of the BIT mass fraction the removal rate of SiO2 remains almost the same, the removalrate of Cu is from 31.6 nm·min－1 to 21.0 nm·min－1, the depth of the dishing pit is from 110 nm to40 nm and the depth of the erosion pit is from 85 nm to 35 nm.
42791 扫描电子显微镜 ( SEM) 测试结果表明，Cu 表面低缺陷，无明显有机物沾污。 Scanning electron microscope (SEM) testresults show that the Cu surface has low defects and no obvious organic contamination.
42792 傅里叶变换红外光谱 ( FTIＲ) 测试结果表明，BIT 能够吸附在 Cu 表面，生成一层钝化膜，从而抑制了 Cu 的腐蚀，降低 Cu 的抛光速率。 Fourier transforminfrared spectrometer (FTIＲ) test results prove that BIT can be adsorbed on the Cu surface, forming apassivation film, inhibiting the corrosion of Cu and reducing the polishing rate of Cu.
42793 超薄体和隐埋氧化层 ( UTBB) 全耗尽绝缘体上硅 ( FDSOI) ( UTBB FDSOI 简称为UTBB) 金属氧化物半导体场效应晶体管 ( MOSFET) 沟道硅膜厚度小于体硅最大耗尽层宽度， The devices modeling method based on the traditional triangular potential well approximation cannot be used for ultra-thin body and buried oxide (UTBB) fully depleted silicon-on-insulator(FDSOI) (UTBB for short) metal oxide semiconductor field effect transistor (MOSFET) .
42794 基于传统三角形势阱近似的器件建模方法已不再适用，必须重新建立基于矩形势阱近似的器件模型。 Because the thickness of Si film in the channel of UTBB is less than the maximum depletion layer width of the bulkSi, the model based on rectangular potential well approximation must be rebuilt.
42795 基于 有 限 高 度 的 矩 形 势 阱 近 似 模 型 求 解 沟 道 薛 定 谔 方 程，建 立 了 单 轴 应 变 硅 UTBBNMOSFET 电子能谷占有率解析模型。 According to the modelof rectangular potential well approximation with finite height, an analytical model about uniaxial strainedSi UTBB NMOSFET electron valley occupancy was built by solving Schrdinger equation approximately.