ID 原文 译文
42756 基于实验结果，研究并提出了复合表面活性剂影响大颗粒数量和表面润湿性，从而减少划伤缺陷的机理。 Based on the experimental results, the mechanism of thecompound surfactant affecting the large particle count and surface wettability was studied and proposed, so as to reduce the scratch defect.
42757 对于提高工业生产晶圆的良品率具有一定参考。 It has certain reference for improving the yield of the wafer in industrialproduction.
42758 为提高电子产品供电性能，设计了一款具有高电源抑制比 ( PSＲＲ) 、超低静态电流、宽输入电压范围的低压差 ( LDO) 线性稳压器。 To improve the power supply performance of electronic products, a low dropout (LDO)linear voltage regulator with high power rejection ratio (PSＲＲ) , ultra-low quiescent current and wide input voltage range was designed.
42759 该电路采用预调节和噪声抵消技术，利用Cadence 工具 SMIC 0. 35 μm CMOS 工艺，完成了整体电路的设计与仿真，并进行了流片。 The design and simulation of the overall circuit were completed by usingthe technology of pre-adjustment and noise cancellation with the Cadence tool and SMIC 0.35 μm CMOSprocess, and the chip was fabricated.
42760 仿真结果显示，LDO 线性稳压器输出线性调整率为 0. 05% /V，负载调整率为 5. 5%，温度系数为 1. 8×10－5 /℃ ; The simulation results show that the output linear regulation rate ofthe LDO linear voltage regulator is 0.05% /V, the load regulation rate is 5.5%, and the temperature coefficient is 1.8×10－5 /℃ .
42761 10 GHz 带宽以内的电源抑制比在低频下能达到 98 dB，静态电流最高仅为 32 μA。 The PSＲＲ within 10 GHz bandwidth can reach 98 dB at low frequency, andthe maximum quiescent current is only 32 μA.
42762 测试结果表明，芯片可以在 3. 3 ～ 40 V 电源电压下正常工作，输出电压为 3. 3 或 5 V，最大负载电流为 150 mA，可应用于 USB 和便携电子产品等多种设备。 The test results show that the chip can operate normallyunder the power supply voltage of 3.3－40 V, the output voltage is 3.3 or 5 V, and the maximum loadcurrent is 150 mA, which can be applied to USB, portable electronic products and other devices.
42763 集成电路 ( IC) 失效分析包含了不同的分析流程，但所有的步骤都是以失效定位和故障隔离作为第一步工作。 Integrated circuit (IC) failure analysis involves different analysis flows, but all stepsstart with failure localization and fault isolation.
42764 失效定位指的是不断地缩小半导体器件故障范围直至可以进行破坏性物理分析的过程。 Failure localization refers to the process of continuouslynarrowing down the fault range of semiconductor devices to the extent where a destructive physicalanalysis can be performed.
42765 根据 IC 的结构特点和分析思路，将整个失效分析流程中失效定位分为封装级失效定位、器件级失效定位和物理分析失效定位。 According to the structure characteristic of IC and analysis approach, the failure localization in the full failure analysis flow is classified into three categories including package levelfailure localization, device level failure localization and physical analysis failure localization.