ID 原文 译文
42696 具有高闭环增益的四级甲乙类放大器优化了输出驱动器的线性度，并减小了电流纹波、电磁干扰以及外围器件个数。 The four-stage class-AB amplifier with a high closed-loop gain can optimize the linearity ofthe output driver, while the current ripple, the electromagnetic interference, and the number ofperipheral devices are reduced.
42697 该输出驱动器在芯片中占的面积约为1.44 mm2，测试及仿真使用的电源电压为 3. 3 ～ 5 V。 The output driver occupied an area of about 1.44 mm2 in the chip, andthe power supply voltage used for simulation and measurement was 3.3－5 V.
42698 结果表明，当甲乙类放大器的输出负载电容为3 300 pF，在典型工艺角以及常温下，其开环直流增益为 99. 21 dB，相位裕度为 58. 24°，增益带宽积为 631 kHz; The results show that whenthe output load capacitance is 3 300 pF at the typical process corner and room temperature, the open-loopDC gain of the class-AB amplifier is 99.21 dB, the phase margin is 58.24°, and the gain-bandwidthproduct is 631 kHz.
42699 当载波频率为 1 MHz 时，丁类放大器的非重叠时间约为 25 ns。 The non-overlap time of the class-D amplifier is about 25 ns at a carrier frequency of1 MHz.
42700 此外，该输出驱动器的输出电压为电源电压的 2 倍，使得功率管效率达到 75%以上。 The output voltage of the output driver is twice that of the power supply voltage, which makes thepower transistor efficiency achieves more than 75%.
42701 面向数字型光隔离放大器芯片应用，设计了一款高分辨率和全集成的接收端电路。 A high-resolution and fully-integrated receiver circuit for digital optical isolation amplifierchip was designed.
42702 基于斩波稳定带隙基准源和数据恢复电路进行电路设计。 The circuit was designed based on chopper-stabilized bandgap reference and data recovery circuit.
42703 带隙基准源采用斩波稳定运算放大器结构，减小了电路在低频的闪烁噪声; The bandgap reference adopted a chopper-stabilized operational amplifier structure to reduce the flick noise of the circuit at low frequency.
42704 数据恢复电路包括二阶无源滤波器和二阶多重反馈滤波器，在保证最大平坦响应的同时，将发送端的脉冲密度调制编码进行恢复，输出高分辨率的模拟信号。 The data recovery circuit included a second-order passive filter and a second-order multiple feedback filter, which can recover the pulse density modulationcode of the transmitter and output high-resolution analog signals while guaranteeing the maximum flat response.
42705 接收端电路采用 CMOS 0. 18 μm 1P6M 工艺进行设计，后仿真结果表明，电源电压为 5 V 时，接收端电路输入信号最大摆幅为 2 V，有效信号带宽为 100 kHz，输出信噪失真比 ( SNDＲ) 达到65. 3 dB，有效位数 ( ENOB) 为 10. 56 bit。 The receiver circuit was designed based on CMOS 0.18 μm 1P6M process.The post-simulationresults show that at a supply voltage of 5 V, the maxium input swing of the receiver circuit is 2 V, the effective signal bandwidth is 100 kHz, the output signal-to-noise-and-distortion-ratio (SNDＲ) achieves65.3 dB, and the effective number of bits (ENOB) reaches 10. 56 bit.