| ID | 原文 | 译文 |
| 42486 | 制备大直径单晶是降低器件成本的重要手段之一。 | The preparation of large-diameter single crystals is one of the important methods toreduce the cost of devices. |
| 42487 | 对于制备大尺寸半绝缘 InP 单晶而言，由于其需要在高温高压环境下生长，随着热场尺寸的增大，炉体中气氛以及熔体中的对流增大，因而易产生孪晶和多晶。 | For the preparation of large-size semi-insulating InP single crystals, due to theneed to grow in a high temperature and high pressure environment, as the thermal field size increases, the atmosphere in the furnace and the convection in the melt increase, thus twin crystals and polycrystalsare easily to be produced. |
| 42488 | 采用液封直拉 ( LEC) 技术，通过多温区热场优化设计，调节各段加热器功率，降低了大尺寸热场温度梯度，提高了热场的对称性和稳定性，获得了平坦的固液界面， | By using the liquid encapsulation Czochralski (LEC) method, through the optimization design of the multi-zones thermal field and adjustment of the power of each section of the heater, the temperature gradient of the large-scale thermal field was reduced, the symmetry and stability ofthe thermal field were improved, and the flat solid-liquid interface was obtained. |
| 42489 | 同时采用平缓放肩工艺抑制孪晶的形成。 | Meanwhile the flatshoulder technique was used to inhibit the formation of twin crystals. |
| 42490 | 重复生长出约 9. 5 kg 的 6 英寸 ( 1 英寸= 2. 54 cm)InP 单晶，直径 6 英寸以上的单晶部分长度大于 67 mm。 | The InP single crystals of 9.5 kgwith a diameter of 6 inch (1 inch = 2.54 cm) were repeatedly grown, and the length of single crystals over6 inch in diameter was greater than 67 mm. |
| 42491 | 测试结果表明，单晶片位错密度小于 1×104 cm－2，电阻率大于 107 Ω·cm。 | The test results show that the dislocation density of the singlecrystal wafer is less than 1×104 cm－2, and the resistivity is greater than 107 Ω·cm. |
| 42492 | 从晶体生长和测试结果可以看出，合适的温度梯度可以使固液界面比较平坦，有效降低 InP 晶体的位错密度，电阻率片内均匀性为 8. 7%。 | The results of crystalgrowth and measurement show that the proper temperature gradient can make the solid-liquid interfaceflat, effectively reduce the dislocation density of the InP crystal, and have good in-wafer uniformity of resistivity of 8.7%. |
| 42493 | 针对 CMOS 器件栅氧化层的早期失效问题，研究了化学气相沉积 ( CVD) 氧化层/热氧化层的双层复合栅结构。 | The double-layer composite gate with chemical vapor deposition (CVD) oxide layer /thermal oxide layer structure was studied to solve the infant mortality issue of gate oxide of CMOS devices. |
| 42494 | 对高温氧化 ( HTO) 层、等离子体增强正硅酸乙酯 ( PETEOS) 和低压正硅酸乙酯 ( LPTEOS) 三种 CVD 氧化层进行了对比， | The properties of high temperature oxide (HTO) layer, plasma enhanced tetraethyl orthosilicate (PETEOS) and low pressure tetraethyl orthosilicate (LPTEOS) were compared. |
| 42495 | 从中优选 HTO 层作为复合栅的 CVD 氧化层， | HTO layer was selected as the best candidate for the CVD oxide layer of the composite gate. |