ID 原文 译文
42126 MMIC 主要由 6 频段振荡电路、控制电路、译码电路等组成。 The MMIC was mainly composed of 6-band oscillationcircuit, control circuit and decoding circuit.
42127 将 10～20 GHz 的频率范围分为 6 个频段覆盖，从而将电调电压控制在 5 V 以内。 The frequency range of 10－20 GHz was divided into 6-band, so as to control the modulating voltage within 5 V.
42128 基于 GaAs 异质结双极晶体管 ( HBT) 2 μm 工艺对所设计的 VCO 进行了流片验证，芯片面积为 3. 4 mm×3. 2 mm。 Based on GaAs heterojunction bipolar transistor (HBT)2 μm technology, the designed VCO was verified by the wafer processing, and the chip area was 3.4 mm ×3.2 mm.
42129 测试结果表明，在室温下，当电源电压为 5 V、电调电压在 0～5 V 时，每个频段 VCO 可覆盖的频率为 9. 58～ 11. 6 GHz、11. 06 ～13. 23 GHz、12. 77～14. 89 GHz、14. 21～16. 48 GHz、16～18. 48 GHz 和 17. 7～20. 17 GHz; The test results show that at room temperature, when the power supply voltage is 5 V and themodulating voltage is in the range of 0－5 V, the frequencies of each band are 9.58－11.6 GHz, 11.06－13.23 GHz, 12.77－14.89 GHz, 14.21－16.48 GHz, 16－18.48 GHz and 17.7－20.17 GHz, respectively.
42130 当电调电压为 2. 5 V、频偏为 100 kHz 时，每个频段 VCO 的相位噪声分别为－91. 8、－90. 5、－90. 3、－90、－88. 2 和－87. 1 dBc /Hz。 When the modulating voltage is 2.5 V and the frequency offset is 100 kHz, the phase noises of the VCO ineach band are －91.8, －90.5, － 90.3, － 90, － 88.2 and － 87.1 dBc /Hz, respectively.
42131 因此，该 6 频段 VCO 覆盖了 10 ～ 20 GHz 的频率范围，且每段VCO 的相位噪声指标良好，可满足低压电子系统的应用需求。 Therefore, the6-band VCO covers the frequency range of 10－20 GHz, and the phase noise index of each band is good, which can meet the application requirements of the low voltage electronic system.
42132 设计了一款低温度系数的自偏置 CMOS 带隙基准电压源电路， A self-bias CMOS bandgap reference voltage source circuit with low temperature coefficient was designed.
42133 分析了输出基准电压与关键器件的温度依存关系，实现了低温度系数的电压输出。 The dependence relationship of the output reference voltage and the temperature ofthe key devices was analyzed, and the voltage output with the low temperature coefficient was realized.
42134 后端物理设计采用多指栅晶体管阵列结构进行对称式版图布局，以压缩版图面积。 Inback-end physical design, a multi-finger transistor-array structure was used for symmetrical layout to compress the layout area.
42135 基于 65 nm /3. 3 V CMOS ＲF 器件模型，在 CadenceIC 设计平台进行原理图和电路版图设计，并对输出参考电压的精度、温度系数、电源抑制比( PSＲＲ) 和功耗特性进行了仿真分析和对比。 Based on 65 nm / 3.3 V CMOS ＲF device model, the circuit and its layout weredesigned on Cadence IC platform.The precision of the output reference voltage, the temperature coefficient, the power supply rejection ratio (PSＲＲ) and the power consumption characteristics were simulatedand compared.