ID 原文 译文
42006 该功率放大器 MMIC 尺寸为 5. 25 mm×2. 10 mm。 The size of the MMIC poweramplifier chip is 5.25 mm×2.10 mm.
42007 在纳米锁存器中，由电荷共享效应导致的多节点翻转 ( MNU) 正急剧增加，成为主要的可靠性问题之一。 Multiple-node upsets (MNUs) induced by the charge sharing effect are increasingrapidly as one of the major reliability issues in nanometer latches.
42008 尽管现有的辐射加固锁存器能够对 MNU 进行较好的容错，但是这些加固锁存器只依赖于传统的冗余技术进行加固，需要非常大的硬件开销。 Although the existing hardened latchesprovide good tolerance for MNUs, the implementation of these hardened latches incurs in considerablehardware penalties, because they rely on conventional redundancy hardening techniques.
42009 基于辐射翻转机制 ( 瞬态脉冲翻转极性) 设计了一种新型抗 MNU 锁存器。 Based on theradiation upset mechanism (the upset polarity of the transient pulse) , a novel type of anti-MNU latchwas designed.
42010 该锁存器可有效减少需保护的节点数 ( 敏感节点数) 和晶体管数，因此可减少电路的硬件开销。 The proposed MNU tolerance latch can effectively reduce the number of nodes need to beprotected (sensitive nodes) , and the number of transistors, thus the hardware overhead of the circuitcan be reduced.
42011 由于至少存在 2 个节点可以保存正确的值，因此任何单节点翻转 ( SNU) 和 MNU 都可以被恢复容错。 The proposed MNU tolerance latch can effectively reduce the number of nodes need to beprotected (sensitive nodes) , and the number of transistors, thus the hardware overhead of the circuitcan be reduced.Any single node upset (SNU) and MNU can be recovered to fault tolerance, because atleast two nodes can retain the values.
42012 基于 TSMC 65 nm CMOS 工艺进行仿真， The circuit was simulated based on TSMC 65 nm CMOS process.
42013 结果显示，设计的加固锁存器的电路面积、传播延迟和动态功耗分别为 19. 44 μm2，16. 96 ps和 0. 91 μW。 The results show that the circuit area, propagation delay and dynamic power consumption of the designedhardened latch are respectively 19.44 μm2, 16.96 ps and 0.
42014 与现有的辐射加固锁存器相比，设计的锁存器具有较小的硬件开销功耗－延迟－面积乘积 ( PDAP) 值，仅为 300. 02。 91 μW, so that it has the smaller powerdelay-area product (PDAP) value (only 300.02) compared with existing hardened latches
42015 以 AlN 材料为陶瓷基材，采用陶瓷绝缘子的射频传输端口结构及陶瓷焊球阵列封装形式，结合多层陶瓷加工工艺，设计并制备了一款可封装多个芯片的 X 波段 AlN 陶瓷外壳。 An X-band AlN multi-chip ceramic package was designed and fabricated by using AlNmaterial as the ceramic substrate, adopting the structure of ＲF transmission port of ceramic insulator andthe package form of the ceramic ball grid array, and combining with the multilayer ceramic processingtechnology.