ID 原文 译文
41956 仿真结果表明，所提方法可有效减小传热退化对模型计算结果的影响，实现对IGBT 模块热行为动态变化的精确模拟， The simulation results show that the proposedmethod is able to reduce the influence of heat transfer degradatio on the model calculation results, and realize the accurate simulation of the dynamic changes of the thermal behavior of IGBT modules.
41957 且结温估计结果相较传统 CTN 模型的更为精确。 Besides, estimation result of the junction temperature is more accurate than that of the traditional CTN model.
41958 针对航天电子控制系统对集成电路的抗辐射需求，设计了一种基于现场可编程门阵列( FPGA) 的全新架构的专用集成电路 ( ASIC) 抗辐射性能评估系统。该系统基于 FPGA 高性能、高速度、高灵活性和大容量的特性， Aiming at the anti-irradiation requirements of the aerospace electronic control system forintegrated circuits, an anti-irradiation performance evaluation system with a novel architecture for application specific integrated circuit (ASIC) based on field programmable gate array (FPGA) was designed by taking advantage of the characteristics of the existing FPGA, such as high performance, high speed, high flexibility and large capacity.
41959 不仅具备传统芯片评估系统的能力，还具备精确判定失效事件发生时刻、被测 ASIC 时序、内部状态及大致的内部路径位置的能力。 While having the capabilities of the conventional chip evaluation systems, the new system is also capable of determining the time of failure event accurately, the tested ASICtiming, internal state and approximate location of internal path.
41960 对该系统进行单粒子翻转 ( SEU) 辐射试验， Single event upset (SEU) performance of the system was evaluated through the critical linear energy transfer threshold.
41961 试验结果表明，在 81. 4 MeV·cm2·mg－1的线性能量转移阈值下，该系统能自动判别没有发生 SEU 事件。 The test results validate thatunder the LET threshold of 81.4 MeV·cm2·mg－1, the system can automatically determine that no SEUevent has occurred on the ASIC chip.
41962 目前，该系统已成功应用于自研高可靠性 ASIC 芯片抗辐射性能的评估。 The developed system has been successfully applied to the antiirradiation performance evaluation of high reliable ASIC chip.
41963 随着 5G 和人工智能等新型基础设施建设的不断推进，单纯通过缩小工艺尺寸、增加单芯片面积等方式带来的系统功能和性能提升已难以适应未来发展的需求。 With the continuous promotion of new infrastructures such as 5G, artificial intelligence, etc, it is difficult to meet the future demands for the development by simply improving system functionality and performance through process dimension reduction, single-chip area increase, etc.
41964 晶圆级多层堆叠技术作为能够突破单层芯片限制的先进集成技术成为实现系统性能、带宽和功耗等方面指标提升的重要备选方案之一。 Waferlevel multilayer stacking technology, as an advanced integration technology which can break through thelimitations of single layer chip, has become one of the most important options to achieve theimprovements of system performance, bandwidth and power consumption.
41965 对目前已有的晶圆级多层堆叠技术及其封装过程进行了详细介绍; The currently available waferlevel multilayer stacking technologies and their packaging processes are described in detail.