ID 原文 译文
41926 LNA 前三级采用电流复用拓扑结构实现低功耗，最后一级采用自偏置结构增加动态范围; The first three stages of the LNA adopted a current multiplexing topological structure toachieve low power consumption, and the last stage used a self-biased structure to increase dynamicrange.
41927 天线端的开关具有较高的功率容量，保证信号经过开关后不会压缩而导致发射支路输出功率不足。 The switch at the antenna end had the higher power capacity, which ensured that the switchwould not cause insufficient output power due to the signal compression.
41928 测试结果显示，电路在 6～18 GHz 频带内，接收支路噪声系数典型值为 3. 7 dB，增益约为 27 dB，1 dB压缩点输出功率典型值大于 7 dBm，功耗约为 140 mW，能耐受 1 W 的连续波输入功率; The test results show that at 6－18 GHz, the receiving branch has a typical noise figure of 3.7 dB, a gain of about 27 dB, a typicaloutput power at 1 dB compression point of more than 7 dBm, a power consumption of about 140 mW, and it can withstand 1 W continuous wave input power.
41929 发射支路饱和输出功率大于30 dBm，功率附加效率典型值为 26%。 The transmitting branch has a saturation outputpower of more than 30 dBm, and a typical power added efficiency of 26%.
41930 智能电网电弧检测片上系统 ( SOC) 芯片需要高性能的锁相环为其提供各种频率的时钟。 Smart grid arc detection system-on-chip (SOC) chips need high performance phaselocked loops to provide clocks of various frequencies.
41931 设计了一种面积小、功耗低、输出频率范围大且锁定精度高的全部基于数字标准单元的全数字锁相环 ( ADPLL) 。 An all-digital phase-locked loop (ADPLL) basedon digital standard units with small area, low power consumption, large output frequency range and highlocking accuracy was designed.
41932 该 ADPLL 基于环形结构的全新的数控振荡器 ( DCO) 设计，通过控制与反相器并联的三态缓冲器的导通数量控制反相器电流进行频率粗调，使 DCO 具有 1. 2 ～ 2. 6 GHz的调节范围。 The ADPLL was designed based on a new digital controlled oscillator(DCO) with ring structure.The inverter current was controlled by controlling the conduction number ofthree-state buffers connected in parallel to the inverter to perform coarse adjustment of frequency so thatthe DCO had an adjustment range of 1.2－2.6 GHz.
41933 通过控制与反相器输出端并联逻辑门的导通数量控制其负载电容进行频率细调，并通过基于夹逼原理的控制字搜索算法找到 DCO 的最佳控制字。 The load capacitance at the output of the inverterwas controlled by controlling the conduction number of parallel logic gates for fine adjustment of frequency.And the best control words of DCO were found through the control words search algorithm based onthe clamping principle.
41934 仿真结果表明，ADPLL 锁定后输出时钟的均方根周期抖动控制在 3 ps 以内，并且其在 55 nm CMOS 工艺下的面积仅为 60 μm×60 μm，功耗为 1 mW 左右。 The simulation results show that the root mean square period jitter of the outputclock after ADPLL locking is controlled within 3 ps, and the area under the 55 nm CMOS process is only60 μm×60 μm, and the power consumption is about 1 mW.
41935 针对现阶段 SiC MOSFET 建模研究无法应用在电机控制系统领域的现状，提出了一种基于 Matlab /Simulink 的 SiC MOSFET 仿真电路模型。 For the current situation that SiC MOSFET modeling research cannot be applied in thefield of motor control system, a simulation circuit model of SiC MOSFET based on Matlab /Simulink wasproposed.