ID 原文 译文
41906 模块集成了数控移相、数控衰减和串并转换等功能，由幅相控制多功能芯片、开关功率放大器芯片、限幅低噪声放大器和控制芯片构成。 The module integrated functions suchas digital control phase shifting, digital control attenuation and serial-to-parallel conversion, and wascomposed of a multi-function chip for amplitude and phase control, a switching power amplifier chip, alimiting low noise amplifier and a control chip.
41907 测试结果显示，在 Ku 波段内，单路发射通道饱和输出功率大于 30 dBm，接收通道增益大于 20 dB，噪声系数小于 3. 5 dB，模块尺寸为 16 mm×16 mm×2. 5 mm。 The test results show that in the Ku-band, the saturatedoutput power of the single transmitting channel is greater than 30 dBm, the gain of the receiving channelis greater than 20 dB, the noise figure is less than 3.5 dB, and the module size is 16 mm×16 mm×2.5 mm.
41908 绝缘体上硅 ( SOI) 工艺具有寄生电容小、速度快和抗闩锁等优点，成为低功耗和高性能集成电路 ( IC) 的首选。 The silicon on insulator (SOI) technology has advantages of small parasitic capacitance, fast speed and anti latch-up, so it has become a preference for the low power consumption and high performance integrated circuits (ICs) .
41909 但 SOI 工艺 IC 更易受自加热效应 ( SHE) 的影响，因此静电放电( ESD) 防护设计成为一大技术难点。 However, the IC based on SOI technology is more susceptible toself-heating effects (SHEs) , so the design of electrostatic discharge (ESD) protection becomes a majortechnical difficulty.
41910 设计了一款基于 130 nm 部分耗尽型 SOI ( PD-SOI) 工艺的数字专用 IC ( ASIC) 。 A digital application specific IC (ASIC) based on 130 nm partially depleted SOI(PD-SOI) technology was designed.
41911 针对 SOI 工艺 ESD 防护设计难点，进行了全芯片 ESD 防护原理分析，通过对 ESD 防护器件、I/O 管脚 ESD 防护电路、电源钳位电路和 ESD 防护网络的优化设计，有效减小了 SHE 的影响。 In view of the ESD protection design difficulty on SOI technology, the principle of whole-chip ESD protection was analyzed.By optimizing the design of an ESD protectiondevice, an I/O pin ESD protection circuit, a power clamp circuit and an ESD protection network, theSHE influence was effectively reduced.
41912 该电路通过了 4. 5 kV 人体模型 ESD 测试，相比国内外同类电路有较大提高，可以为深亚微米 SOI 工艺 IC ESD 防护设计提供参考。 The circuit has passed a 4.5 kV human body model ESD test, and it is greatly improved compared with other similar circuits at home and abroad.It can provide a reference for the IC ESD protection design based on deep submicron SOI technology.
41913 绝缘体上硅 ( SOI) 工艺具有寄生电容小、速度快和抗闩锁等优点，成为低功耗和高性能集成电路 ( IC) 的首选。 The silicon on insulator (SOI) technology has advantages of small parasitic capacitance, fast speed and anti latch-up, so it has become a preference for the low power consumption and high performance integrated circuits (ICs) .
41914 但 SOI 工艺 IC 更易受自加热效应 ( SHE) 的影响，因此静电放电( ESD) 防护设计成为一大技术难点。 However, the IC based on SOI technology is more susceptible toself-heating effects (SHEs) , so the design of electrostatic discharge (ESD) protection becomes a majortechnical difficulty.
41915 设计了一款基于 130 nm 部分耗尽型 SOI ( PD-SOI) 工艺的数字专用 IC ( ASIC) 。 A digital application specific IC (ASIC) based on 130 nm partially depleted SOI(PD-SOI) technology was designed.