ID 原文 译文
41886 为满足电子器件散热、密封和信号传输优良的需求，陶瓷基板以较高的热导率、与半导体材料相匹配的热膨胀系数、致密的结构和较高的机械强度等特性得到广泛的应用。 In order to meet the requirementsof excellent heat dissipation, sealing and signal transmission of electronic devices, ceramic substrateshave been widely used for their high thermal conductivity, matched thermal expansion coefficient withthat of semiconductor materials, compact structure and high mechanical strength and other properties.
41887 首先综述了不同陶瓷基板材料的性能、发展历史和新进展，分析了各自的优缺点; First, the properties, development history and new progress of different ceramic substrate materials arereviewed, and their advantages and disadvantages are analyzed.
41888 然后综述了陶瓷基板的制备工艺，对多层共烧陶瓷技术进行了详细介绍，并简述了陶瓷基板的应用; Then, the preparation process ofceramic substrate is summarized, the multi-layer co-fired ceramic technology is introduced in detail, andthe application of ceramic substrate is briefly described.
41889 最后指出了陶瓷基板的研究方向和面临的挑战。 Finally, the research direction and challenges ofceramic substrate are given.
41890 智能电网电弧检测片上系统 ( SOC) 芯片需要高性能的锁相环为其提供各种频率的时钟。 Smart grid arc detection system-on-chip (SOC) chips need high performance phaselocked loops to provide clocks of various frequencies.
41891 设计了一种面积小、功耗低、输出频率范围大且锁定精度高的全部基于数字标准单元的全数字锁相环 ( ADPLL) 。 An all-digital phase-locked loop (ADPLL) basedon digital standard units with small area, low power consumption, large output frequency range and highlocking accuracy was designed.
41892 该 ADPLL 基于环形结构的全新的数控振荡器 ( DCO) 设计， The ADPLL was designed based on a new digital controlled oscillator(DCO) with ring structure.
41893 通过控制与反相器并联的三态缓冲器的导通数量控制反相器电流进行频率粗调，使 DCO 具有 1. 2 ～ 2. 6 GHz的调节范围。 The inverter current was controlled by controlling the conduction number of three-state buffers connected in parallel to the inverter to perform coarse adjustment of frequency so that the DCO had an adjustment range of 1.2－2.6 GHz.
41894 通过控制与反相器输出端并联逻辑门的导通数量控制其负载电容进行频率细调，并通过基于夹逼原理的控制字搜索算法找到 DCO 的最佳控制字。 The load capacitance at the output of the inverterwas controlled by controlling the conduction number of parallel logic gates for fine adjustment of frequency.And the best control words of DCO were found through the control words search algorithm based onthe clamping principle.
41895 仿真结果表明，ADPLL 锁定后输出时钟的均方根周期抖动控制在 3 ps 以内，并且其在 55 nm CMOS 工艺下的面积仅为 60 μm×60 μm，功耗为 1 mW 左右。 The simulation results show that the root mean square period jitter of the outputclock after ADPLL locking is controlled within 3 ps, and the area under the 55 nm CMOS process is only60 μm×60 μm, and the power consumption is about 1 mW.