ID 原文 译文
41586 首先阐述了泄漏电流的来源; Firstly, thesource of the leakage current is introduced.
41587 然后介绍了影响 OFET 静态功耗的最主要因素是栅极泄漏电流， Then, it is introduced that the most important factor affectingthe static power consumption of OFETs is the gate leakage current.
41588 总结了近年来降低 OFET 栅极泄漏电流的主要方法，如构建多层结构的栅介质、开发新型栅介质材料和交联栅介质材料; The main methods to reduce the gateleakage current of OFETs in recent years are summarized, such as building multi-layer gate dielectrics, developing new gate dielectric materials and cross-linking gate dielectric materials.
41589 最后对降低 OFET 泄漏电流的方法进行了展望。 Finally, the methodsto reduce the leakage current of OFETs are prospected.
41590 提出了一种高速低延时 8 bit /10 bit 解码电路结构，采用四路并行通道同时处理输入数据，每一路具有 K 码检测、输入数据查错功能，能够在输入四路 10 bit 数据后的一个时钟周期内正确完成解码。 A high speed and low latency 8 bit /10 bit decoding circuit structure was proposed, which adopted four parallel channels to process input data at the same time.Each channel has the functions of K-code detection and input error checking, and input 10 bit data of the four channels can be correctly decoded within one clock cycle.
41591 所设计的解码电路通过搭建的通用验证方法学系统完成系统级功能验证，并基于 65 nm 工艺库进行综合、布局和布线，解码电路的面积为 1 449 μm2。 The designed decoding circuit was verified by the universal verification methodology system which built for the system-level functional verification.Based on 65 nmprocess library synthesis, layout and wiring, the area of the decoding circuit is 1 449 μm2.
41592 后仿真结果显示，解码电路的最高工作频率达 415 MHz，四路可支持最高 16. 6 Gibit /s 的串行数据传输速率，满足JESD204B 协议标准推荐的最高传输速率 12. 5 Gibit /s 的要求。 The postsimulation results show that the maximum working frequency of the decoding circuit is up to 415 MHz, and the four channels can support 16.6 Gibit /s serial data transmission rate, which meets the requirement of the JESD204B protocol standard for the highest transmission rate of 12.5 Gibit /s.
41593 将该解码电路用于支持 JESD204B协议的高速数模转换器电路中，经测试，其传输速率最高达 10. 5 Gibit /s。 It is applied inthe high speed digital-to-analog converter circuit to support JESD204B protocol, and the tested transmission rate is up to 10.5 Gibit /s.
41594 介绍了一种基于反熔丝的抗辐照精密校频专用集成电路 ( ASIC) 设计方案，可应用于频率控制系统，实现精密的频率调节。 A design scheme of anti-irradiation precise frequency adjustment application specific integrated circuit (ASIC) based on anti-fuses was introduced, which could be applied to realize precisefrequency adjustment in frequency control systems.
41595 该 ASIC 以反熔丝可编程数字电压阵列为核心，集成数字通信协议接口、一次性可编程 ( OTP) 随机存储器 ( ＲAM) 和译码器等功能，通过数字控制方式实现精密电压的产生和调节。 Taking anti-fuse programmable digital voltage array asthe core, the ASIC integrated functions such as digital communication protocol interface, one time programmable (OTP) random access memory (ＲAM) and encoder to produce and adjust precise voltagethrough digital control.