| ID | 原文 | 译文 |
| 41546 | 通过优化腔长与量子阱总增益之间的匹配参量及对光波导的优化设计，提高了芯片注入饱和点; | By optimizing the matching parameters betweenthe cavity length and the total gain of the quantum well and the optimal design of optical waveguide, theinjection saturation point of the chip was increased. |
| 41547 | 通过提升注入水平提高了芯片输出功率。 | The output power of the chip was improved by increasing the injection level. |
| 41548 | 芯片测试结果显示，25 ℃时阈值电流为 13 mA，斜率效率为0. | The test results of the chip show that the threshold current is 13 mA at 25 ℃, the slope efficiency is 0. |
| 41549 | 38 W/A，输出功率为 102 mW@ 300 mA，边模抑制比为 51 dB@ 50 mW，ＲIN 为－160 dB /Hz@ 300 mA。 | 38 W/A, the output power is 102 mW@ 300 mA, the side-mode suppression ratio is 51 dB@ 50 mW, and the ＲIN is －160 dB /Hz@ 300 mA. |
| 41550 | 该芯片具备高输出功率、低 ＲIN、低阈值电流、高斜率效率的特点。 | The chip has the characteristics of highoutput power, low ＲIN, low threshold current and high slope efficiency. |
| 41551 | SiC MOSFET 分立器件的并联结构已在中大功率应用中广泛使用，为了充分利用并联的优势，需解决并联动态电流不均衡问题。 | The parallel structure of SiC MOSFET discrete devices has been widely used in mediumand high power applications.To make full use of the advantages of the parallel structure, the problem ofimbalanced dynamic current in the parallel structure should be solved. |
| 41552 | 在 SiC MOSFET 特性参数中，阈值电压是影响并联动态均流特性最主要的参数。 | Among the characteristic parameters of SiC MOSFETs, threshold voltage is the most important parameter affecting the dynamic currentbalancing characteristics of the parallel structure. |
| 41553 | 通过建立SiC MOSFET双管并联的电路模型，探究了并联动态电流不均衡的补偿策略，推导了阈值电压对 SiC MOSFET 开关管动态均流程度影响的公式。 | By establishing the circuit model of double-transistorparallel SiC MOSFETs, the compensation strategy of parallel dynamic current imbalance wasinvestigated, and a formula was derived which illustrated the influence of threshold voltage on the dynamic current balance degree of SiC MOSFET switches. |
| 41554 | 建立了含寄生电感的双管并联电路模型，提出了两种双管并联动态电流不均衡的无源补偿策略，即基于共源极寄生电感的补偿策略以及基于开尔文源极电感和功率源极寄生电感并联的补偿策略。 | A double-transistor parallel circuit model withparasitic inductance was established.Two passive compensation strategies for imbalanced dynamic currentin double-transistor parallel structure were proposed, that is, the compensation strategy of commonsource parasitic inductance and the compensation strategy of Kelvin source inductance in together withpower source parasitic inductance. |
| 41555 | 通过仿真比较了两种无源补偿策略下的开关总损耗。 | The total switching losses of two passive compensation strategies werecompared through simulation. |