ID 原文 译文
41506 该功率放大器MMIC电路采用三级放大拓扑结构进行设计； The power amplifier MMIC circuit was designed with a three-stage amplifier topology.
41507 采用高低阻抗微带传输线进行阻抗匹配和片上功率合成； The high and low impedance microstrip transmission lines were used for impedance matching and on-chip power synthesis.
41508 采用介质电容和薄膜电阻进行偏置网络设计，实现稳定工作和低损耗输出。 The dielectric capacitor and film resistor were used for bias network to realize stable operation and low loss output.
41509 经测试，在55～65 GHz频带内，漏极工作电压+20 V、栅极工作电压-2.3 V的偏置条件下，在占空比20%、脉宽100μs脉冲状态时，该功率放大器MMIC的饱和输出功率达到3 W以上，功率附加效率达到22%; The test results show that in the 55－65 GHz frequency range, under the bias conditions of drain operation voltage of + 20 V and gate operation voltage of － 2.3 V, the power amplifier MMIC achieves a saturated output power of greater than 3 W and a power added efficiency of 22% in the pulse state with a duty cycle of 20% and a pulse width of 100 μs.
41510 连续波状态时，其饱和输出功率达到2.5 W以上，60 GHz时最高功率达到3 W。 In the continuous wave state, its saturated output power reaches greater than 2. 5 W and a maximum power of 3 W at 60 GHz.
41511 与消费类电子产品相比，用于继电保护的集成电路 ( IC) 面临着更为严苛的静电放电 ( ESD) 环境，需要高可靠性的电源钳位 ESD 电路，但这会给芯片带来较大的泄漏功耗。 Compared with consumer electronics, integrated circuits (ICs) for relay protection needhigh reliability power clamp electrostatic discharge (ESD) circuits to face more severe ESD environment, but it will bring large leakage power consumption to the chip.
41512 针对继电保护电路的 ESD 需求，提出了一种低漏电型电源钳位 ESD 电路，减小了 ESD 触发模块的电容，有效防止了继电保护下快速上电和高频噪声带来的误触发。 According to the ESD requirements of therelay protection circuit, a low leakage current power clamp ESD circuit was proposed to reduce the capacitor of the ESD trigger module and effectively prevent the false trigger caused by rapid power on andhigh-frequency noise.
41513 利用电流镜结构获得大的等效ESD 触发模块电容，保证了泄放晶体管的导通时间。 The current mirror structure was used to obtain a large equivalent ESD triggermodule capacitance, which ensured the turn-on time of discharge transistor.
41514 利用钳位二极管技术，减小钳位电路触发模块的泄漏电流。 A clamp diode technologywas used to reduce the leakage current of the clamp circuit trigger module.
41515 基于标准 65 nm CMOS 工艺对电源钳位 ESD 电路进行了流片验证， The power clamp ESD circuitwas verified based on standard 65 nm CMOS process.