ID 原文 译文
41176 热感应产生的极化电势可以改变压电半导体结构内的力电物理量，这在人工智能、微机电系统(MEMS)中极具应用价值。 The polarization potential generated by thermal variation can change the mechanical and electrical physical quantities in the piezoelectric semiconductor structure, which is of valuable application in artificial intelligence and MEMS.
41177 文章针对温度梯度作用下的氮化镓(GaN)压电pn结，采用二维压电半导体多场耦合方程和精确的热电物理边界条件，数值分析了温度梯度改变对GaN热压电pn结内极化强度、电势、电场、载流子分布及电流等物理场的影响。 By utilizing a developed twodimensional model together with the accurate thermoelectric physical boundary conditions, it is systematically investigated the temperature gradient-dependent physical fields such as polarization, electric potential, electric field, carrier distribution and current in a GaN piezoelectric pn junction.
41178 结果表明:由于温度梯度场和极化电荷之间存在耦合，热压电pn结电学性能对温度梯度高度敏感， It is found that, due to the coupling between the thermal-gradient fields and polarization charges, the electromechanical field of a piezoelectric pn junction has a quick response to thermal-gradient.
41179 由温度改变产生的热感应极化电荷可以有效调节该结构的开启电压和载流子传输特性， Furthermore, gate voltage and carrier transport characteristics can be effectively tuned with thermal-induced and piezoelectric charges.
41180 这为操控与温度相关的智能异质结器件电流传输提供了新的方法和理论指导。 This may provide an alternative approach and theoretical guidance to manipulate the carrier transport in intelligent heterojunction devices.
41181 针对MEMS器件背面引线的需求，提出了一种基于玻璃通孔(TGV)加工方法的10.16cm(4inch)圆片衬底的制备工艺流程。 Aiming at the demand of the backside leads of MEMS devices, aprocess for the fabrication of 10.16 cm(4 inch)wafer substrates based on the through-glass-vias(TGV)processing method is presented.
41182 首先深硅刻蚀导电硅片，然后将硅片和玻璃片阳极键合，随后将键合后的玻璃-硅圆片经高温加热，使玻璃填充至硅片中， Firstly, the conductive silicon wafer was deeply etched, then anodic bonding was performed between the silicon wafer and the glass wafer, and then the bonded glass-silicon wafer was heated at a high temperature to fill the glass into the silicon wafer.
41183 再依次研磨抛光玻璃-硅圆片的正面玻璃和背面硅，直至硅与嵌入玻璃在同一平面，最后得到了厚度为258μm的4inch圆片衬底， Then the front glass and back silicon of the glass-silicon wafer was grinded and polished until the silicon and the embedded glass were on the same plane.Finally, a 4 inch substrate with a thickness of 258μm was obtained.
41184 其轮廓算术平均偏差、轮廓最大高度、微观不平度十点高度的平均值分别为13，71和49nm。 The arithmetic mean deviation of the profile, the maximum profile height and the microscopic unevenness are 13, 71 and 49 nm respectively.
41185 此外，测得圆片中硅导通柱电阻率为0.023Ω·cm。 In addition, the measured resistivity of the silicon via in the wafer is 0.023Ω·cm.