ID 原文 译文
40996 针对现有NAND闪存垃圾回收算法对回收效率和数据冷热分离考虑的不足，提出了一种基于无效页年龄的NAND闪存垃圾回收算法。 A new NAND flash memorygarbage collection algorithm based on invalid page age was proposed to solve the problems of the existing NAND flash garbage collection algorithm, which considered the efficiency of the collection and the separation of hot and cold data.
40997 该算法提出了新的回收块选择策略，用无效页年龄计算回收代价，同时使用静态磨损的方法保证了物理块的磨损均衡。 This algorithm proposeda new victim block selection strategy which calculated collection cost use number and age of invalid pages, while use static wear to ensure wear leveling.
40998 此外，算法重新定义了逻辑页数据热度计算公式，提出使用动态调节的阈值将有效数据分为热数据、次热数据、次冷数据和冷数据，将不同类型的数据迁移到不同的空闲块中，有效实现了逻辑页数据的冷热分离。 In addition, the algorithm redefines the heat calculation formula of the logical page data, and proposes to divide the valid data into hot data, sub-hot data, sub-cold data and cold data by using the dynamically adjusted threshold value.Different types of data are transferred to different idle blocks, which effectively realizes the separation of cold and hot of the logical page data.
40999 实验结果表明，与GR，CB，CAT，FaGC，FaGC+算法相比，该算法取得了最小的垃圾回收代价以及更好的磨损均衡效果。 The simulation results show that compared with GR, CB, CAT, FaGC and FaGC+ algorithms, the proposed algorithm achieves minimum collection cost and better results in wear leveling.
41000 近年来，RISC-V在处理器领域的大行其道，不仅仅在于其开源可扩展的指令集架构属性，同时也得益于加州大学伯克利分校为其量身打造的敏捷化设计语言Chisel，极大降低了处理器设计门槛。 In recently years, RISC-V′s popularity in the field of processors is not only due to its open-source and extensible instruction set architecture attributes, but also thanks to Chisel, an agile design language tailored by UC Berkeley, greatly reducing the threshold of processor design.
41001 本文基于Chisel语言设计实现了一款带有扩展指令协处理器的多核RISC-V芯片， A multi-core RISC-V chip with extended instruction coprocessor based on Chiselis designed and implemented in this paper.
41002 相对于传统的硬件设计语言，将硬件IP的设计与集成周期压缩50%以上， Compared with the traditional hardware design language, the design and integration time of hardware IP is compressed by more than 50%.
41003 并且依靠丰富的模板资源，能够快速完成拓扑互连、时序分割、跨时钟域转换等影响处理器整体性能的全局性优化设计，将芯片验证与实现的迭代周期缩短30%以上， At the same time, relying on rich template resources, it can quickly complete the global optimization design that affects the overall performance of the processor, such as topology interconnection, timing segmentation, and cross-clock domain conversion, reducing the iteration time of chip verification and implementation by more than 30%.
41004 为开源处理器敏捷化开发探索了行之有效的技术手段。 The open-source processor agile development has explored effective technical means.
41005 在高速大容量的存储系统中，传输通道为实时的双向链路，微控制器无法实时感知存储设备的状态，需要存储设备主动发起数据的传输。 In a high-speed and large-capacity storage system, the transmission channel is a real-time bidirectional link, and the microcontroller cannot sense the state of the storage device in real time, and the storage device needs to initiate data transmission actively.