ID 原文 译文
40546 在时钟方案约束的布局区域内预先计算和缓存路径信息，并应用深度优先搜索策略搜索正确的电路布局布线结果. The path information is pre-calculated and cached within the layout region constrained by the clock scheme, and the depth-first search strategy is applied to search for the correct circuit placement routing results.
40547 该算法采用C++编程语言实现，仿真结果验证了算法的正确性. The algorithm is implemented in C++ programming language, and simulation results verify the correctness of the proposed algorithm.
40548 二值化神经网络(Binary Neural Network， BNN)具有单比特数据位宽的特点，可以很好地解决传统卷积神经网络中存在大量数据量以及计算量的问题. The single-bit data width characteristic of Binary Neural Network(BNN) can tackle large-scale-data and huge-amount-calculation in Convolution Neural Network(CNN).
40549 为了进一步加速BNN的正向推导并降低所需功耗，提出一种基于FPGA的完全二值化卷积神经网络加速器，其中输入图片以及边缘填充都进行了二值化处理， In order to further accelerate the forward inference of BNN and reduce the required power consumption, a fully binarized neural network accelerator based on FPGA is proposed, in which the input image and edge padding are all binarized.
40550 并且通过分时重用行卷积查找表的方式跳过其中的冗余计算. And the accelerator skips the redundant calculations by reusing the Row Convolution LUT(RC-LUT) in a time-sharing way.
40551 在Xilinx的ZCU102 FPGA开发板上对所设计的加速器进行评估， 结果表明加速器的运算速度可以达到3.1 TOP/s，并且可以达到144.2 GOPS/KLUT的资源效率转换比以及3 507.8 GOPS/W的能效转换比. By implementing on Xilinx's ZCU102 FPGA, this accelerator can achieve a Performance of more than 3.1 TOP/s, an Area Efficiency of 144.2 GOPS/KLUT, and a Power Efficiency of 3 507.8 GOPS/W.
40552 为了解决超高速无采保流水线型ADC中比较器失调(包含孔径误差与静态比较器失调)对整体性能的影响问题，本文提出了一种后台数字校准方法. In order to resolve the defect of comparator offset(including aperture error and static comparator offset) degrading the overall performance of high speed SHA-less pipelined ADC, an effective background digital calibration method is proposed.
40553 该方法通过在数字域对输出余差进行统计完成误差的检测，并在模拟域调节校准DAC完成误差的校准. The detection of calibration is implemented by collecting the output residual voltage in digital domain, and the correction of calibration is implemented by controlling and configuring the DAC in analog domain.
40554 校准基于余差均值之差和极值之和，分别对孔径误差和静态比较器失调进行迭代提取，避免了来自其他非理想因素的影响，提高了高频信号下ADC整体性能，有效提高了校准的稳定性. The calibration uses the difference of the mean values and the sum of extremums of the residueto characterize the aperture error and static comparator offset respectively, which avoids the disadvantages brought by other non-idealities in calibration, improves the ADC performance for high speed input, and improves the stability effectively.
40555 该方法应用于一款2.5 GS/s 12 bit ADC中，并基于FPGA进行实现.根据实际测试结果在输入信号频率为1.913 GHz时，校准后SNDR提高了8 dB. The proposed calibration method is applied in a 2.5 GS/s12 bit ADC based on FPGA implementation. In this work, simulation and prototype verification are carried out to validate the practicability of the proposed method.The SNDR is improved by over 8 dB@1.913 GS/s based on the measurement.