ID 原文 译文
40536 通过自检测技术快速进行故障检测和定位，进而利用当班表决实现四余度的升降级管理与重构.通过建立可靠性模型进行分析， Through the self-detection technology, the fault detection and location can be carried out quickly, and then the promotion and degradation management and reconstruction of the four-redundancy can be realized by the on-duty voting, and the reliability model can be established for the analysis.
40537 四模并联模式5年(约4.5万小时)的可靠度高达0.995. The reliability of four-mode parallel mode in 5 years(about 45, 000 hours) is as high as 0.995.
40538 该技术已成功应用于某天地往返飞行器. The technology has been successfully applied to a space shuttle.
40539 为了进一步提高浮点乘法器的性能，缩短浮点乘法器关键路径延时，提出了一种基于新型4-2压缩器和5-2压缩器的混合压缩结构. In order to further improve the performance of Floating-Point Multiplier and shorten the critical path delay of Floating-Point Multiplier, a hybrid compression structure based on new 4-2 compressor and 5-2 compressor is proposed.
40540 在Xillinx的xc7a35tcsg324开发板上，基于该结构实现了IEEE754标准的32位浮点乘法器. On the xc7 a35 tcsg324 development board of xillinx, the 32-bit Floating-Point Multiplier of IEEE754 standard is implemented based on this structure.
40541 相较于现有的压缩方式，提出的新型压缩结构相较于现有的压缩方式，所使用的LUT资源减少了45，关键路径延时减少了0.004 ns. Compared with the existing compression methods, the LUT resource and critical path delay are reduced by 45 and 0.004 ns respectively.
40542 与传统浮点乘法器相比，关键路径延时由6.022 ns缩短至4.673 ns，提升了浮点乘法器的运算性能. Compared with the traditional Floating-Point Multiplier, the critical path delay is reduced from 6.022 ns to 4.673 ns, which improves the performance of the Floating-Point Multiplier.
40543 量子点元胞自动机(QCA)被认为是克服传统CMOS局限性的一种极有前景的解决方案. Quantum-Dot Cellular Automata(QCA) is considered asa promising solution to overcome the limitations ofconventional CMOS.
40544 近年来，QCA电路的自动化设计工具的开发越来越受到研究者的关注，布局和布线算法则是其中至关重要的一环. Recently, the development of automated design tools for QCA circuits has attracted more and more attention from researchers, where the placement and routing algorithm is a critical step.
40545 算法设计的关键问题是时钟方案和时钟同步性约束.本文提出了一种门级布局和布线算法， The key issue of an algorithm design is the constraints of a clock scheme and clock synchronization. Agate-level placement and routing algorithm is proposed.