ID 原文 译文
25885 为此，本文提出了基于多层注意力表示的音乐推荐模型，利用用户属性信息和歌曲内容信息从多维度学习歌曲表征，挖掘用户与歌曲之间的偏好关系。 Therefore, we propose a hierarchical attention representation model (HARM) to improve the music recommendation quality. HARM utilizes attributes of users and contents of music to learn music representation from the perspective of multi-dimension and mine the preference relationship between user and music．
25886 为了区分用户对歌曲多域特征的差异性偏好，设计了用户特征依赖的注意力网络;为了区分不同历史行为对用户偏好的差异性，挖掘用户行为的时序依赖关系，设计了歌曲依赖的注意力网络。 In order to mine users' differential preference on music's multi-field feature, a user feature-dependent attention network is designed. In addition, in order to mine the impacts of different historical behavior on user preference and learn sequential dependency of user's, a music-dependent attention network is designed．
25887 最后，利用 Softmax 函数计算用户对候选歌曲的偏好分布并产生推荐。 Finally, recommendation is generated by using a softmax function to calculate the preference distribution of users on candidate songs．
25888 在 30Music 和 MIGU 数据集上的实验结果表明，相比目前的推荐模型，本文提出的模型在 Recall 和 MRR 均得到了显著提升。 The experimental results on 30Music and MIGU datasets shows that, comparing with the existent recommendation models, HARM can gain significant improvement on Recall and MRR．
25889 传统的 PLL(Phase Locked Loop)电路受限于环路参数的选定，其相位噪声与抖动特性已经难以满足大阵列、高精度 TDC(Time-to-Digital Converter)的应用需求。 The traditional PLL (Phase Locked Loop) circuit is limited by the selection of loop parameters and its phase noise and jitter characteristics have been difficult to meet the application requirements of large array and high precision TDC (Time-to-Digital Converter)．
25890 本文致力于 PLL 环路带宽的优化选取，采取 TSMC 0. 35μmCMOS 工艺实现了一款应用于 TDC 的具有低抖动、低噪声特性的锁相环(Phase Locked Loop，PLL)电路，芯片面积约为0. 745mm × 0.368mm。 This paper devotes to the optimal selection of PLL loop bandwidth and a PLL circuit withlow noise and low jitter characteristics is designed. The chip area is approximately 0.745mm × 0. 368mm．
25891 实际测试结果表明，在外部信号源输入 15. 625MHz 时钟信号的条件下，PLL 输出频率可锁定在250. 0007MHz，频率偏差为 0. 7kHz，输出时钟占空比为 51. 59% ，相位噪声为 114.66dBc/Hz@ 1MHz，均方根抖动为4. 3ps，峰峰值抖动为 32. 2ps。 The actual test results of the chip show that under the condition of external signal source input 15. 625MHz clock signal and the PLL outputfrequency can be locked at 250.0007MHz. The frequency deviation is 0. 7kHz. The duty cycle of the output clock is 51. 59% and the phase noise is -114. 66dBc/Hz@ 1MHz. The RMS jitter of the clock is 4. 3ps and the peak-to-peak jitter is 32. 2ps．
25892 锁相环的相位噪声显著降低，输出时钟的抖动特性明显优化，可满足高精度阵列 TDC 的应用需要。 The phase noise of the phase-locked loop is significantly reduced and the jitter characteristics of the output clock are significantly optimized, which can basically meet the application needs of the array TDC．
25893 针对传统天线测量数据处理中粗差剔除和定权不合理问题，提出了一种结合粗差剔除和一次范数最小法定权的天线反射面多仰角测量数据处理方法。 Aiming at the unreasonable problem of gross error elimination and weight determination in traditional antenna measurement data processing, a method for multi-elevation antenna measurement data processing is proposed, which combines gross error elimination and weighting way of L1-norm least method．
25894 首先，根据反射面自重变形的特点，通过构造统计量对粗差点予以剔除，提高了测量数据的可靠性;其次，顾及测量点的变形特点，引入了抗差估计中的一次范数最小法对不同变形点进行定权，解决了等权最小二乘拟合的“虚假面型”问题。 Firstly, according to the characteristics of reflectorgravity deformation, the gross error was eliminated by constructing statistics, which improved the reliability of measurement data． Secondly, referring to the deformation characteristics of measurement points, the L1-norm least method in robust estimation was introduced to determine the weights of different deformation points, so as to solve the "false fitting surface" problem of equal-weight least square fitting．