ID 原文 译文
23725 同样，该方法也对提高自偏置PLL 噪声性能有指导意义。 It can also give guidelines on how to further improve the noise performance of SBPLL.
23726 为了提高显著性算法对不同类图像的适用性以及结果的完整性，该文提出一种基于自适应阈值合并的分割过程与新的背景选择方法相结合的显著性检测算法。 In order to improve the applicability for different types of image and integrity of the results, a saliency detection algorithm is proposed. It combines the adaptive threshold merging with a new background selection strategy.
23727 在分割过程中，生成相邻区块的 RGB 以及 LAB 共六通道融合的颜色差值序列，采用区块面积参数的反比例模型生成自适应阈值与颜色差值序列进行对比合并。 In the segmentation process, the color difference sequence is obtained by the selective fusion of RGB and LAB of adjacent blocks. Adaptive threshold is generated by inverse proportion model of block area parameter. Merging progress is done after the adaptive threshold comparison with the color difference sequence.
23728 在背景选择过程中，根据局部区域背景-主体-背景的相对位置关系线索，得到背景区域，再对结果进行边缘优化。 In the background selection process, background regions are obtained by the local relative position of background-subject-background in the local area. The experimental results are optimized for edge.
23729 该算法与其它算法相比得到的显著图不需要外接其他阈值算法即生成二值图，自适应阈值合并能排除复杂环境中的物体细节，专注于同等级大小物体的显著性对比。 Compared with other algorithms, the saliency map of two values obtained does not need external threshold algorithm in this paper. Adaptive threshold merging can eliminate the details of objects in complex environments and can focus on the saliency comparison of the same level size objects.
23730 为了降低集成电路的软错误率，该文基于时间冗余的方法提出一种低功耗容忍软错误锁存器。 To reduce the soft error rate of the circuit, this paper proposes a low power soft error tolerant latch based on time redundancy technology.
23731 该锁存器不但可以过滤上游组合逻辑传播过来的 SET 脉冲，而且对 SEU 完全免疫。 The proposed latch can fully tolerate the Single Event Upset (SEU) when particles strike on internal nodes. Furthermore, it can efficiently mask the input Single Event Transient (SET).
23732 其输出节点不会因为高能粒子轰击而进入高阻态，所以该锁存器能够适用于门控时钟电路。 Its output node will not enter a high impedance state when a particle strikes on internal nodes, so the proposed latch can be applied to clock-gating circuits.
23733 SPICE 仿真结果表明，与同类的加固锁存器相比，该文结构仅仅增加 13.4%的平均延时，使得可以过滤的 SET 脉冲宽度平均增加了 44.3%，并且功耗平均降低了 48.5%，功耗延时积(PDP)平均降低了 46.0%，晶体管数目平均减少了 9.1%。 Detailed SPICE simulations are done to evaluate the proposed latch circuit and previous latch circuits designed in the literatures. Compared with other soft error tolerant latches, the proposed latch introduces 13.4% delay overhead on average. While it can achieve 44.3% increase in filterable SET pulse width, 48.5% reduction in power, 46.0% reduction in Power Delay Product (PDP), and 9.1% reduction in transistor numbers on average.
23734 光纤网络和无线接入技术结合的 FiWi 网络可提供高容量、灵活以及低基础设施成本的无线接入能力。由于 FiWi 网络中客户端业务量一般具有不稳定性，很难提前有效预测，高效公平的动态带宽分配(DBA)机制具有重要作用。 The integration of optical and wireless technologies, denoted as Fiber-Wireless (FiWi) networks, can provide not only high capacity but also flexible wireless access ability with less infrastructure deployment. Since data traffic generated in FiWi networks usually experiences unstable and unpredictable, it is difficult to perform traffic prediction in advance. An effective and fair Dynamic Bandwidth Allocation (DBA) scheme plays an important role.