ID 原文 译文
20745 译码过程中，译码器首先通过第1层存储信息采用置信传播(BP)算法译码完成，随后一些未被成功译出的信息再通过第2层存储信息进行填补。 Contrarily, in the decoding process, the decoder first uses the Belief Propagation (BP) algorithm to decode by the first information, and then correct some unrecovered bits by the second information.
20746 仿真结果表明，将CPRSD-H编译码算法应用于认知无线电系统中，能够显著降低LT码的误比特率(BER)，提高次用户有效吞吐量以及加快LT码编译码速度。 Simulation results show thatthe proposed method CPRSD-H and application to cognitive radio systems can significantly reduce the BitError Rate (BER) of LT codes, the goodput performance of secondary users and the encoding and decodingspeed of LT codes.
20747 针对现有环形振荡器物理不可克隆函数(ROPUF)设计存在的可靠性和唯一性不高，导致在应用时安全性较差的问题，该文提出面向ROPUF的统计模型，定量分析了可靠性和唯一性的影响因素，发现增大延迟差能够提高可靠性，减小环形振荡器(RO)单元间的工艺差异可以提高唯一性。 The existing Ring Oscillator (RO) Physical Unclonable Function (ROPUF) design has low reliabilityand uniqueness, resulting in poor application security. A statistical model for ROPUF is proposed, the factorsof reliability and uniqueness are quantitatively analyzed, it is found that the larger delay difference can improvethe reliability, and the lower process difference between RO units can improve the uniqueness.
20748 根据该模型结论，设计了基于mesh拓扑结构的动态RO单元，结合RO阵列频率分布特性，设计了一种新的频率排序算法，以增大延迟差和减小RO单元的工艺差异，从而提高ROPUF的可靠性和唯一性。 According to theconclusion of the model, a dynamic RO unit is designed based on the mesh topological structure. Incombination with the frequency distribution characteristics of the RO array, a new frequency sorting algorithmis designed to increase the delay difference and reduce the process variation of the RO unit, thereby improvingthe reliability and uniqueness of ROPUF.
20749 结果表明，与其他改进设计的ROPUF相比，所提设计的可靠性和唯一性具有显著优势，可达到99.642%和49.1%，且受温度变化的影响最小。 The results show that compared with other improved ROPUFdesigns, the reliability and uniqueness of the proposed design has significant advantages, which can reach99.642% and 49.1%, and temperature changes affect minimally them.
20750 安全性分析证明，该文的设计具有很强的抗建模攻击能力。 It is verified by security analysis that theproposed design has strong anti-modeling attack capabilities.
20751 该文提出一种用于电荷域流水线模数转换器(ADC)的高精度输入共模电平不敏感采样保持前端电路。 A high precision common mode level insensitive sample and hold front-end circuit for charge domain pipelined Analog-to-Digital Converter (ADC) is proposed.
20752 该采样保持电路可对电荷域流水线ADC中由输入共模电平误差引起的共模电荷误差进行补偿。 The sample and hold circuit can be used to compensate the common mode charge errors caused by the variation of input common mode level in charge domain pipelined ADCs.
20753 所提出的高精度输入共模电平不敏感采样保持电路被运用于一款14位210 MS/s电荷域ADC中，并在1P6M 0.18 μm CMOS工艺下实现。 Based on the proposed sample and hold circuit, a 14-bit 210 MS/s charge domain pipelined ADC is designed and realized in a 1P6M 0.18 μm CMOS process.
20754 测试结果显示，该14位ADC电路在210 MS/s条件下对于30.1 MHz单音正弦输入信号得到的无杂散动态范围为85.4 dBc，信噪比为71.5 dBFS，而ADC内核功耗仅为205 mW，面积为3.2 mm2。 Test results show the 14-bit 210 MS/sADC achieves the signal-to-noise ratio of 71.5 dBFS and the spurious free dynamic range of 85.4 dBc, with30.1 MHz input single tone signal at 210 MS/s, while the ADC core consumes the power consumption of205 mW and occupies an area of 3.2 mm2.