ID 原文 译文
20605 首先，基于变压器模型，从无线电能传输的角度推导了近场密集标签间的互阻抗表达式。 Firstly, based on the transformer model, the mutual impedance expressions of the NF dense tags are derived from the perspective of radio energy transmission.
20606 然后，结合近场电感耦合型标签，通过建立电磁仿真模型间接获取有关电气参数值。 Then, the electrical parameter values are obtained indirectly by establishing the electromagnetic simulation model combining with the NF inductance coupling tag.
20607 最后，验证推导公式并从影响双标签间互阻抗的环境因素角度去研究UHF RFID近场频率偏移问题。 Finally, the derivation formula is verified and UHF RFID NF frequency shift is studied from the perspective of environmental factors that affect the mutual impedance between the two tags.
20608 测试结果表明，当标签间距小于30 mm时，推导的互阻抗表达式应用于频率偏移计算误差范围为1.6～7.3 MHz。 The test results show that the derived mutual impedance expression is applied to the frequency offset calculation with error range in 1.6～7.3 MHz when the tags’ spacing is less than30 mm.
20609 研究结果为基于标签间互阻抗预估UHF RFID近场标签间的互耦效应问题提供了参考依据。 The results provide a reference for studying the mutual coupling effect between UHF RFID NF tags based on the mutual impedance between tags.
20610 二叉决策图(BDD)是一种数据结构，广泛应用于数字电路的逻辑综合、测试和验证等领域。 Binary Decision Diagrams (BDD) is a data structure that can be used to describe a digital circuit.
20611 将BDD每个结点映射成2选1数据选择器(MUX)可得到BDD映射电路。 By replacing each node in a BDD with a 2-to-1 Multiplexer (MUX), a BDD can be mapped to a digital circuit.
20612 该文提出一种BDD映射电路的面积和延时优化方法。 An area and delay optimization method on BDD mapped circuit is presented.
20613 首先把待优化电路转换成BDD形式，然后逐一搜索BDD中存在的菱形结构，进而通过路径优化实现结点的删减和控制变量的更改，并将所得结果BDD映射成MUX电路，最后用多个MCNC基准电路进行测试， A traditional Boolean circuit is converted into BDD form, and then diamond structure constructed by nodes is searched in the BDD, corresponding nodes are deleted and control signals of the modified nodes are updated by paths optimization, finally, the result BDD is mapped to a MUX circuit. The proposed method is test by a number ofMicroelectronics Center of North Carolina (MCNC) Benchmarks.
20614 将该文方法与经典综合工具BDS, SIS等方法相比较，BDD总结点数比BDS减少了55.8%，映射电路的面积和延时比SIS分别减小了39.3%和44.4%。 Compared with the classical synthesis toolsSequential Interactive System (SIS) and BDD-based logic optimization System (BDS), the average number ofnodes by the proposed methods is 55.8% less than that of BDS, and average circuit’s area and delay arereduced by 39.3% and 44.4% than that of the SIS, respectively.