ID 原文 译文
19465 其次在随机预言机模型下证明了该方案是安全的。 Secondly, it is proved that the proposed scheme is safe under the random oracle model.
19466 最后效率分析表明，该方案在实现原方案所有的功能的基础上同时降低了计算代价。 Finally, the efficiency analysis shows that the proposed scheme reduces the computational cost while realizing all the functions of the original scheme.
19467 针对D2D通信的资源分配问题，该文研究了D2D信道选择与功率控制策略。 Considering the resource allocation problem for Device-to-Device (D2D) communications, a channel selection and power control strategy for D2D communications is investigated.
19468 在保证蜂窝用户服务质量(QoS)的前提下，提出一种基于启发式的D2D信道选择算法，为系统内的D2D用户找到合适的信道复用资源。 On the premise of guaranteeingthe Quality of Service (QoS) of cellular users, a heuristic based D2D channel selection algorithm is proposed tofind the suitable channel reusing resources for D2D users in the system.
19469 同时，利用拉格朗日对偶方法求解得到D2D用户最优传输功率。 At the same time, the optimal transmission power of D2D users is obtained by using the Lagrange dual method.
19470 仿真结果表明当蜂窝用户与多对D2D用户共享信道资源时能够大幅度提升系统平均吞吐量。 Simulation resultsdemonstrate that when the cellular user shares channel resources with multiple pairs of D2D users, the systemthroughput can be dramatically improved.
19471 在相同条件下，该算法的性能要明显优于现有算法。 The performance of this algorithm outperforms the exiting algorithms under the same conditions.
19472 该文针对3维FPGA (3D FPGA)芯片存在的散热问题，提出具有低热梯度特征的互连网络通道结构 To solve the problem of heat dissipation in Three Dimensional Field Programmable Gate ArrayTechnology (3D FPGA), an interconnect channel architectural design method with low thermal gradient feature is proposed.
19473 该文建立了3D FPGA的热阻网络模型；对不同类型的通道线对3D FPGA的热分布影响进行了理论分析和热仿真； A thermal resistance network model is established for the 3D FPGA, and theoretical studies and thermal simulation experiments are carried out on the influence of different types of channels on the thermal performance of 3D FPGA.
19474 提出了垂直方向通道网络非均匀分布的3D FPGA通道结构，实验表明，与给定传统FPGA互连通道结构相比，采用所提方法实现的3D FPGA设计架构能够降低76.8%的层间最高温度梯度，10.4%的层内温度梯度。 Further, non-uniform vertical direction channel structures of 3D FPGA areproposed. Experiments indicate that 3D FPGA designed using the method proposed can reduce the maximum temperature gradient between different layers by 76.8% and the temperature gradient within the same layer by10.4% compared with the traditional channel structure of 3D FPGA.