ID 原文 译文
16545 该文综述了基于深度学习的关节点行为识别方法，按照网络主体的不同将其划分为卷积神经网络(CNN)、循环神经网络(RNN)、图卷积网络和混合网络。 In this paper, the methods of action recognition using joints based on deep learning inrecent years are summarized. According to the different subjects of the network, it is divided into ConvolutionalNeural Network(CNN), Recurrent Neural Network(RNN), graph convolution network and hybrid network.
16546 卷积神经网络、循环神经网络、图卷积网络分别擅长处理的关节点数据表示方式是伪图像、向量序列、拓扑图。 The representation of joint point data that convolution neural network, recurrent neural network and graph convolution network are good at is pseudo image, vector sequence and topological graph.
16547 归纳总结了目前国内外常用的关节点行为识别数据集，探讨了关节点行为识别所面临的挑战以及未来研究方向，高精度前提下快速行为识别和实用化仍然需要继续推进。 This papersummarizes the current data sets of action recognition using joints at home and abroad, and discusses thechallenges and future research directions of behavior recognition using joints. Under the premise of highprecision, rapid action recognition and practicality still need to be further promoted.
16548 亚阈值电路是低功耗重要发展方向之一。 Sub-threshold circuit is an important development direction of low power consumption.
16549 随着电源电压降低，晶圆代工厂提供的标准单元电路性能容易受噪声和工艺偏差的影响，已经成为制约亚阈值芯片的瓶颈。 With thereduction of power supply voltage, the performance of standard cell circuits provided by foundries is susceptibleto noise and process deviations, which has become a bottleneck restricting sub-threshold chips.
16550 该文提出一种基于施密特触发(ST)与反向窄宽度效应(INWE)的亚阈值标准单元设计方案。 The high-robustsub-threshold standard cells are proposed in this work.
16551 该方案首先利用ST的迟滞效应与反馈机制，在电路堆叠结点处添加施密特反馈管以优化逻辑门、减少漏电流、增强鲁棒性； The Schmitt Trigger (ST) and Inverse Narrow WidthEffect (INWE) are used to improve the performance, leakage, robust of the logic gates.
16552 然后，采用INWE最小宽度尺寸与分指版图设计方法，提高电路的开关阈值与MOS管的驱动电流； Then, the INWE minimum width size and finger layout methods are used to increase the switching threshold of the circuit and the drive current of transistor.
16553 最后，在TSMC 65 nm工艺下构建标准单元的物理库、逻辑库和时序库，完成测试验证。 Finally, the standard cell library is designed and verified with TSMC 65 nmprocess.
16554 实验结果表明，所设计的亚阈值标准单元与文献相比，功耗降低7.2%～15.6%，噪声容限提升11.5%～15.3%，ISCAS测试电路的平均功耗降低15.8%。 The experimental results show that the power of designed standard cells is reduced about 7.2%～15.6%,the noise margin is improved about 11.5%～15.3%, and the average power of ISCAS test circuit is reduced about 15.8%.