ID 原文 译文
16485 该文基于DNA折纸术，设计了一个通过DNA折纸结构的自组装求解图的顶点着色问题的方法。 Based on the DNA origami technique, a method for the graph vertex coloring problem is proposed viathe self-assembly of DNA origami structures.
16486 利用DNA折纸术可以构建出具有特定形状的DNA折纸结构。 Utilizing the DNA origami technique different DNA origamistructures with specific shapes are constructed.
16487 这些结构可以用来编码图的顶点和边，由于这些结构具有粘性末端，因此可以通过特异的分子杂交组装成为代表了不同的图的顶点着色方案的高级结构。 These structures are utilized to encode the information of agraph’s vertices and edges, and because these structures have sticky ends, so they can assemble to advancedstructures which stands for different answers of the graph vertex coloring problem via specific molecularhybridization.
16488 利用DNA-纳米颗粒共聚体的属性和电泳等实验方法，可以筛选出正确的符合条件的图的顶点着色方案。 Utilizing the property of DNA nanoparticle conjugation and electrophoresis as well as otherexperimental methods, the correct answer of the graph vertex coloring problem can be detected.
16489 该方法是一种高度并行的方法，可以极大地降低求解图的顶点着色问题的复杂度。 This method ishighly parallel, and can greatly reduce the complexity of the graph vertex coloring problem.
16490 水平集算法因其出色的性能，在图像分割领域中得到了广泛的应用。 The level set algorithm is widely used for image segmentation due to its high accuracy.
16491 同时，与基于深度学习的图像分割算法相比，水平集算法不需要训练数据，大幅降低了数据标记带来的工作量。 In addition, compared to the deep learning-based image segmentation methods, the level set algorithm can be implemented without training data, which reduces significantly the labeling efforts.
16492 然而，目前水平集算法主要是基于软件开发，涉及大量复杂的计算，以及计算的多次迭代，导致较高的处理延时与功耗。 However, the normal level set algorithm is still developed using software, involving complex computation with a large number of pixels and iteration sand causing long processing time and large power consumption.
16493 为了加快水平集算法的处理速度和降低功耗，该文提出了一种基于FPGA的水平集图像分割算法加速器，其中包含4个设计创新点：任务级并行处理、图像分块像素级并行处理、全流水线处理架构、分时复用的梯度和散度算子处理。 In this work, an FPGA-based level set hardwareaccelerator is proposed for image segmentation. The proposed hardware accelerator contains four designcomponents: task-level parallel processing, image splitting processing, fully-pipelined processing architecture,and time-multiplexed gradient and divergence processing engine.
16494 实验结果表明，与在CPU上执行的水平集算法相比，该文提出的硬件加速器处理速度提升10.7倍，功耗仅为2.2 W。 Based on the experimental results, the proposed hardware accelerator achieves up to 10.7 times acceleration compared to the level set algorithm executing on the CPU, with only 2.2 W power consumption.