ID 原文 译文
16475 实验证明，该文提出的能效概率模型平均经过2300次迭代输出最终结果，且预测准确率达到92.7%。 Experiments prove that the energy efficiency probability model in this paper outputs thefinal result after 2300 iterations on average, and the prediction accuracy rate reaches 92.7%.
16476 根据最高能效概率模型，对密码专用处理器设计空间进行探索，获取满足高能效需求的密码专用处理器运算单元集合，以扩展指令的方式将其集成到开源通用64位RISCV处理器核心Araine中，提出高能效密码专用处理器体系结构。 According to thehighest energy efficiency probability model, a collection of computing units that meet high energy efficiencyrequirements can be obtained, and they are integrated into the open source general-purpose 64 bit RISCVprocessor core named Ariane. A dedicated processor for energy-efficient cryptography is built.
16477 将该处理器在CMOS 55 nm工艺下进行逻辑综合，结果表明，该文提出的RISCV密码专用处理器与扩展前相比面积增大了426874 mm2，关键延迟增加了0.51 ns，完成密码算法总时间面积积增幅之和为0.46，执行常见密码算法能效比在1.61～35.16 Mbps/mW范围内。 The processor is synthesized under the CMOS 55 nm process, and the results show that compared with Ariane, the area of the proposed cryptographic processor increases by 426874 mm2, the key delay increases by 0.51 ns, and the sum of the increasing total time area of the cryptographic algorithm is 0.46, the energy efficiency ratio of common cryptographic algorithms is within the range of 1.6～35.16 Mbps/mW.
16478 针对单光子探测盖革雪崩焦平面读出电路应用，基于全局共享延迟锁相环和2维H型时钟树网络，该文设计一款低抖动多相位时钟电路。 A low-jitter multi-phase clock generation circuit is designed based on a global shared Delay LockedLoop (DLL) and a two-dimensional H-shaped clock tree network for Geiger-mode avalanche focal plane arrayapplications.
16479 延迟锁相环采用8相位压控延迟链、双边沿触发型鉴相器和启动-复位模块，引入差分电荷泵结构，减小充放电流失配，降低时钟抖动。 The DLL adopts an eight-phase voltage-controlled delay chain, a double-edge trigger phasedetector and a start reset module. A differential charge pump structure is introduced to reduce the currentmismatch between charging and discharging and lower the clock timing jitter.
16480 采用H时钟树结构，减小大规模电路芯片传输路径不对称引起的相位差异，确保多路分相时钟等延迟到达像素单元。 H clock tree structure is involved to diminish the phase variation induced by the asymmetry of the transmission route for large scale integrated circuit, ensuring an equal delay of the multi-channel split-phase clock signal to the pixel unit.
16481 采用0.18 mm CMOS工艺流片，测试结果表明，延迟锁相环锁定频率范围150～400 MHz。锁定范围内，相位噪声低于–127 dBc/Hz@1 MHz，时钟RMS抖动低于2.5ps，静态相位误差低于65 ps。 The locking frequency range of 150～400 MHz, phase noises below -127 dBc/Hz at 1 MHz offset, RMS timing jitter of below2.5 ps and static phase error below 65 ps are achieved based on a 0.18 mm digital-analog hybrid CMOS technology.
16482 毫米波雷达的距离分辨率和最大可工作距离通常受雷达射频信号带宽和发射功率的限制，具有宽工作带宽、高输出功率、高灵敏度、高精度相位控制的毫米波雷达芯片是实现高性能毫米波雷达系统的关键。 The range resolution and maximum working distance of millimeter-wave radar are usually limited by the RF bandwidth and transmitted power. Millimeter-wave radar front-end chip with wide bandwidth, hightransmitted power, high sensitivity and high-precision phase control is crucial to millimeter-wave radar systemto achieve high performance.
16483 毫米波雷达芯片的设计难点主要集中在阻抗匹配、噪声降低、功率提升、相位控制等方面。 The difficulties of millimeter-wave radar chips mainly focus on impedancematching, noise reduction, transmitted power increase, phase control, etc.
16484 因此，该文针对毫米波雷达前端芯片设计难点的关键解决技术进行探讨和综述。 Therefore, this article discusses andsummarizes the key technique to solution the difficulties of millimeter-wave radar front-end chips.