ID 原文 译文
15365 传统的TMR只能针对单个故障提供一次保护,而将三模冗余结构进行分区可以增强其环境适应性。 Traditional TMR provides protection against a single fault at a time, while partitioned TMR provides improved availability.
15366 研究了一种将配置刷新和分区三模冗余结合的方法,并采用PRISM工具进行模型验证,结果表明该方法可以增强系统的可用性。 A recovery methodol-ogy to combine partitioned TMR and configuration scrubbing is presented in this paper, and the results show that the improvement in availability is achieved by the proposed methodology.
15367 针对毫米波通信的高速率和低时延设计要求,设计实现1/2码率(2,1,7)卷积码的低时延译码。 Aiming at the high-speed and low-delay design requirements of millimeter wave communications, this paper designs low-delay decoding of convolutional codes with 1/2 code rate( 2, 1, 7).
15368 采用高度并行优化实现框架、低延时的最小值选择方式,获得Viterbi硬判决译码算法的输出。 A highly parallel optimization implementation framework and a low-latency minimum selection method are adopted to obtain the output of the Viterbi hard decision decoding algorithm.
15369 利用基于Xilinx公司的Artix7-xc7a200t芯片综合后,译码器的数据输出延时约89个时钟周期,最高工作频率可达203.92 MHz。 After synthesis using the Artix7-xc7a200t chip based on Xilinx, the data output delay of the decoder is about 89 clock cycles, and the highest operating frequency can reach 203. 92 MHz.
15370 结果表明,该译码器可支持吉比特级的数据传输速率,实现了低延时、高速率的编译码器。 The results show that the decoder can support gigabit-level data transmission rates, and realizes a low-latency, high-rate codec.
15371 高速电力线载波信道噪声环境复杂,而现有设备难以对载波信道噪声采集和测量分析。 The noise environment of HPLC channel is complex, but the existing equipment is difficult to collect and analyze the channel noise.
15372 为此,提出了一种高速电力线载波信道分析模块,可实现现场噪声高精度样本采集、信道衰减特性测试等功能,并且可在实验室测试环境中进行噪声回放,实现现场环境的真实模拟。 Therefore, this paper proposes a HPLC channel analysis module, which can realize the functions of high-precision sample collection, channel attenuation characteristic test, etc., and can play back the noise in the laboratory test environment to re-alize the real simulation of the field environment.
15373 首先介绍了分析模块的硬件架构组成,描述了FPGA逻辑电路的状态机设计及嵌入式软件设计方案,最后对研制的样机进行了测试,结果表明信道分析模块能够满足设计要求的所有功能,解决了高速电力线载波通信芯片对抗噪声技术研究和现场运维测试的难题。 Firstly, the hardware architecture of the analysis module is introduced, the state machine design of FPGA logic circuit and embedded software design are described. Finally, the prototype is tested. The results show that the channel analysis module can meet all the functions of the design requirements, and solve the problems of HPLC communication chip anti noise research and field maintenance test.
15374 针对某项目多通道数字变换器的设计,提出了一种高可靠性、高精度的模数转换方案。 In this paper, a high-reliability and high-precision analog-to-digital conversion scheme is proposed for the design of a multi-channel digital converter in a project.