ID 原文 译文
15215 基于VIS 0.4μm BCD工艺，使用Hspice进行了仿真验证。 Based on VIS 0. 4 μm BCD process, Hspice is used for simulation and verification.
15216 仿真结果表明：电路能够将-12～12 V的电压比较得到正确的数字信号。 The simulation results show that the circuit can get the correct digital signal by comparing the voltage of-12 ～ 12 V.
15217 在常温即25℃，TT工艺角下，迟滞门限为108.9 mV。 The hysteresis threshold was 108. 9 mV at room temperature( 25 ℃) and TT process corner.
15218 在温度从-40℃～125℃变化时，迟滞门限电压变化小于9.16 mV，温度系数为0.055 5 mV/℃。 When the temperature changes from-40 ℃ to 125 ℃, the change of hysteresis threshold voltage is smaller than 9. 16 mV, the temperature coefficient is 0. 055 5 mV/℃.
15219 基于Micro-Electro-Mechanical System(MEMS)工艺，采用双层谐振腔滤波结构，分析并设计了一种基于MEMS的硅基Substrate Integrated Waveguide (SIW)双通带宽带带通滤波器芯片。 This paper analyzes and designs a silicon based substrate integrated waveguide( SIW) dual passband broadband bandpass filter chip based on Micro-Electro-Mechanical System(MEMS) process with double layer resonant cavity filter structure.
15220 设计的滤波器芯片在21.25～29 GHz以及43～47.5 GHz双通带频带内插入损耗小于3 dB，相对带宽分别为30%以及10%，带外抑制度大于20 dB，并且在双通带间产生了零点，尺寸仅为4.2 mm×1.1 mm×0.8 mm。 The designed filter chip has an insertion loss of less than 2 dB in the 23 ～ 29 GHz and 43 ～ 47 GHz dual passband bands with relative bandwidths of 23 % and 9 %, respectively, and an out-of-band suppression of more than 20 dB, and generates a zero point between the dual passbands with a size of only 4. 2 mm × 1. 1 mm × 0. 8 mm.
15221 该滤波器是平面堆叠结构，具有体积小、频带宽、易集成等优点，有较好的应用价值。 The filter is a planar stacked structure, with the advantages of small size,wide band and easy integration, which has good application value.
15222 时间交织型SAR ADC对包括电容失配在内的通道间失配较敏感，其中电容失配既包括通道内的失配也包括通道间的失配，是影响时间交织型SAR ADC性能的重要因素。 The time-interleaved SAR ADC is sensitive to mismatch between channels. The key factor is the capacitor mismatch, both in channel and between channels.
15223 为了提升时间交织型SAR ADC的性能，基于对SAR ADC中DAC电容失配对时间交织型SAR ADC影响的分析，结合单通道低速工作SAR ADC的电容校正方法，提出了一套适用于时间交织型SAR ADC的电容校正方法，实现了超过9 dB的SFDR和超过2.5 dB的SNDR性能提升。 This paper analyzes the impacts of capacitor mismatches in DAC of SAR( Successive-Approxima-tion-Register) ADC on time-interleaved SAR ADC. For improving performance of time-interleaved SAR ADC, a calibration tech-nique based on calibration of capacitor mismatches in single low-speed SAR ADC is proposed, which results in improvement of SFDR( Spurious Free Dynamic Range) exceed 9 dB and SNDR( Signal to noise distortion ratio) exceed 2. 5 dB.
15224 为了满足当前电源模块高效大功率的要求，针对氮化镓器件设计一款高频驱动电路，并搭建形成高频高效的电源模块。 In order to meet the high efficiency and high power requirement of current power supply module, this paper designs a high frequency drive circuit for gallium nitride device, and builds a high frequency and high efficiency power supply module.