ID 原文 译文
15005 经测试，新客户端提高了3～7倍的指令执行效率，同时也保证了复杂场景下的内存安全以及数据准确性。 After testing,the new client has improved instruction execution efficiency by 3～7 times, while also ensuring memory safety and accuracy in complex scenarios.
15006 HDLC信号链路是国际标准化组织(ISO)制定的高级数据链路的控制规程(High Level Data Link Control,HDLC)。 The HDLC signal link is the high level data link control(HDLC) developed by the international organization for standardization(ISO).
15007 遵循HDLC标准数据链路层规范，采用硬件描述语言Verilog HDL实现了一种基于并行结构的HDLC搜帧解封装电路，并采用System Verilog技术搭建验证平台，随机生成HDLC数据帧来验证设计正确性。 The article follows the HDLC standard data link layer specification,uses the hardware description language Verilog HDL to implement a parallel structure-based HDLC frame search and decapsulation circuit,and uses System Verilog technology to build a verification platform,and randomly generates HDLC data frames to verify the correctness of the design.
15008 使用Modelsim软件仿真波形，在仿真过程中，对于净荷区数据长度为10个字节的HDLC数据帧，解码器电路工作完成需要16个时钟周期，兼顾了处理速度和灵活性。 Using Modelsim software to simulate waveforms,during the simulation process,for HDLC data frames with a payload area of 10 bytes,the decoder circuit requires 16 clock cycles to complete the work, taking into account processing speed and flexibility.
15009 使用QuartusII软件综合，在Altera CycloneV器件上，电路使用了8块自适应逻辑模块ALM,24个寄存器，35个引脚。 Using QuartusⅡ software synthesis, on Altera CycloneV devices,the circuit uses 8 adaptive logic modules ALM,24 registers, and 35 pins.
15010 随着嵌入式系统小型化和模拟数字/数字模拟转换器(ADC/DAC)性能需求的日益增长，如何在减小系统体积和功耗的前提下，提高ADC/DAC信号传输的可靠性，增加功能可配置性和信号处理可重构性，成为一大难题。 With the growing demand of embedded system miniaturization and the performance of analog-to-digital/digital-to-analog converter(ADC/DAC), it is a big problem how to improve the reliability of ADC/DAC signal transmission, increase the function configurability and signal processing reconfigurability on the premise of reducing system volume and power consumption.
15011 为此，设计了一款基于FPGA的系统级封装(SiP)原型验证平台，该SiP基于ADC+SoC+DAC架构，片上系统(SoC)内部以PowerPC470为处理器，集成了多种通用外设接口和可重构算法单元。 Thus, this paper designs a system in package (SiP) prototype verification platform based on FPGA,used to verify the feasibility and reliability of this SiP architecture. This SiP is based on the ADC+SoC+DAC architecture, PowerPC470 is the internal processor of system on chip(SoC), which integrates various common peripherals and the reconfigurable algorithm unit.
15012 在搭建的FPGA平台上进行裸机IP和基于可重构IP的ADC/DAC设计功能的验证。 The design and function verification of bare machines IP and ADC/DAC based on reconfigurable IP are carried out on the built FPGA platform.
15013 通过软硬件协同验证实验，证明了该类SiP架构能够有效降低走线延时和噪声干扰，提高信号传输的可靠性，丰富的外设接口提高了ADC/DAC的可配置性，集成的可重构算法模块增加了ADC/DAC信号处理可重构性，为后续集成更多器件该类型SiP的设计和验证奠定了一定的技术基础。 It is verified that this SiP can effectively reduce routing deley and noise interference to improve the transmission reliability of signal,rich peripheral interface improves configurability of ADC/DAC,integrated reconfigurable algorithm increases the reconfigurable performance of signal processing through software and hardware co-verification experiment,laying a basic technical foundation for later SiP design and testing for integrating more devices.
15014 采用标准0.18μm工艺，设计了一种能改变抽取率并且适应不同信号带宽的应用于Sigma-Delta模数转换器的数字抽取滤波器。 Based on the standard 0.18 μm process,a digital decimation filter applied to the Sigma-Delta analog-to-digital converter is designed,which can change the decimation rate and adapt to different signal band widths.