ID 原文 译文
13574 通过MTSS仿真计算得出：相同尺寸时, 环圈结构基波耦合阻抗远高于螺旋线基波耦合阻抗；在10.65GHz处, 环圈结构饱和增益比螺旋线饱和增益高10.28dB；在10GHz处, 环圈结构的起振电流比螺旋线起振电流高2.35A, 起振长度为53mm。 Through MTSS simulation, we find that the fundamental-wave coupling impedance of the ring-loop structure is much higher than that of the Helix;at 10.65GHz, the saturation gain of the ring-loop structure is 10.28dB higher than that of the Helix;at 10GHz, the star-oscillating current of the ring-loop structure is 2.35Ahigher than that of the Helix, and the staroscillating length of the ring-loop structure is 53mm longer than that of the Helix with the same size.
13575 仿真结果表明, X波段内环圈结构和螺旋线的起振电流随着频率的升高而降低, 环圈结构的起振电流和起振长度为螺旋线的起振电流和起振长度的两倍以上；使用CST仿真分析得出了环圈结构中的圈宽度和圈高度对环圈高频特性影响的一般规律。 Besides, in X-band, the simulation results show that the star-oscillating current of the ring-loop structure and the Helix decreases with increasing frequency, the star-oscillating current and the star-oscillating length of the ring-loop structure are twice over that of the Helix;the general rule of influence of ring width and ring height on the high frequency characteristics of the ring-loop is obtained by CST.
13576 文中结果表明环圈结构性能优良且不易起振, 在大功率行波管中具有广阔的应用前景。 The result show that the ring-loop has good performance and is not likely to generate backward-wave oscillations, which has broad application prospect in high power traveling wave tube.
13577 提出了一种宽带低相噪频率合成器的设计方法。 A design method of wideband low phase noise frequency synthesizer is proposed in the paper.Digital phase locked loop (PLL) technology is adopted.
13578 采用了数字锁相技术, 该锁相技术主要由锁相环 (phase locked loop, PLL) 芯片、有源环路滤波器、宽带压控振荡器和外置宽带分频器等构成, 实现了10～20GHz范围内任意频率输出, 具有输出频率宽、相位噪声低、集成度高、功耗低和成本低等优点。 The frequency synthesizer is mainly composed of PLL chip, active loop filter, wideband voltage controlled oscillator (VCO) and external wideband divider.The PLL can realize any frequency output in 10—20GHz.And it has the advantages of wide output frequency, low phase noise, high integration, low power consumption and low cost.
13579 最后对该PLL电路杂散抑制和相位噪声的指标进行了测试, 测试结果表明该PLL输出10GHz时相位噪声优于-109dBc/Hz@1kHz, 该指标与直接式频率合成器实现的指标相当。 The phase noise test curves are presented, and the experimental results show that the phase noise of the PLL is better than that of-109dBc/Hz@1kHz when the output is 10GHz, which is very close to the phase noise of the direct frequency synthesizer.
13580 针对低信噪比 (signal-to-noise ratio, SNR) 下, 经典波达方向估计性能下降的问题, 提出将信号的四阶累积量与期望最大化 (expectation maximization, EM) 算法相结合的波达方向估计算法。 Aiming at the problem of low estimation performance of classical direction of arrival (DOA) estimation under low signal-to-noise ratio (SNR) , this paper proposes a DOA estimation algorithm which combines the fourth-order cumulant of signal with the expectation maximization algorithm.
13581 该方法引入隐含变量进行更新迭代, 并求隐含变量的四阶累积量, 构造关于待估波达方向的极大似然函数从而求解出信号的波达方向角。 The method introduces an implicit variable to update and iterate, and finds the fourth-order cumulant of the implicit variable. The maximum likelihood function of the estimated direction of arrival is constructed so as to obtain the direction-of-arrival of the signal.
13582 仿真结果表明：本文算法能有效地抑制高斯噪声对信号参数估计的影响, 同时能利用迭代来提高估计精度。 The simulation results show that the proposed algorithm can effectively suppress the influence of Gaussian noise on the signal parameter estimation. Meanwhile, the algorithm using iterative updating can improve the estimation accuracy.
13583 在低SNR时其估计性能优良, 具有很好的稳定性和分辨率, 有利于高分辨地估计信号的波达方向。 It has good performance in low signalto-noise ratio (SNR) estimation, good stability and resolution, which is beneficial to the high-resolution estimation of DOA.