ID 原文 译文
12304 通过 Silvaco TACD 计算机仿真平台，对具有阶梯变掺杂基区的 SiC 光控晶体管与常规均匀掺杂基区的 SiC 光控晶体管的性能进行了对比分析。 By using the Silvaco TACD computer simulation platform，the performances of theSiC optically controlled transistor with step-shaped gradually doped base and the SiC optically controlled transistor with conventional uniform base were compared and analyzed．
12305 结果表明，阶梯变掺杂基区结构可以产生加速载流子输运的感生电场，缩短基区渡越时间，改善器件开通性能。 The results indicate that the stepshaped gradually doped base can induce an electric field to accelerate the carrier transport，reduce the base transit time，and improve the turn-on performance of the device．
12306 该结构提高了 SiC 光控晶体管的电流增益并缩短开通时间，但同时会损失部分关断性能。 The structure improves the currentgain and reduces the turn-on time of SiC optically controlled transistor，meanwhile，losing partial turn-off performance.
12307 仿真结果显示，当变掺杂区浓度梯度为 4. 5×1020 cm－4时，电流增益与开通时间改善幅度分别达到 18%和 32%，关断时间增加了约 22%。 The simulation results show that when the concentration gradient of the gradually doped baseis 4. 5×1020 cm－4，the improvements of current gain and turn-on time are 18% and 32%，respectively，and the turn-off time improves about 22%．
12308 基于 GF 8HP 0. 12 μm BiCMOS 工艺设计并实现了一款应用于相控阵系统的具有低幅度均方根 ( ＲMS) 误差的单片集成 5 ～ 40 GHz 5 bit 数控衰减器。 A 5－40 GHz 5 bit monolithic digital attenuator with low root mean square ( ＲMS) amplitude error for phased array systems was designed and implemented based on GF 8HP 0. 12 μm BiCMOSprocess.
12309 该衰减器采用桥 T 和单刀双掷( SPDT) 开关结构，其中的 NMOS 开关管通过采用体端悬浮技术，改善了衰减器在全部衰减态下插损的平坦度，降低了衰减器的插损，提高了衰减器的线性度。 Bridged-T and single-pole-double-throw ( SPDT) switches were adopted in the attenuator． TheNMOS transistor switch used the body-floating technique to optimize the flatness of the insertion loss underall attenuation states，decrease the insertion loss and improve the linearity of the attenuator.
12310 测试结果显示，在 5 ～ 40 GHz 频段内，该 5 bit 数控衰减器的插损最小值为 5. 7 dB，最大值为 14. 2 dB，幅度均方根误差小于0. 39 dB，相移均方根误差小于 5. 7°，1 dB 压缩点输入功率大于+ 11 dBm，芯片核心面积为0. 86 mm×0. 39 mm。 The measured results show that from 5 GHz to 40 GHz，the minimum insertion loss of the 5 bit digital attenuator is 5. 7 dB and the maximum value is 14. 2 dB． The amplitude ＲMS error is less than 0. 39 dB，and thephase shift ＲMS error is less than 5. 7°． The input power at 1 dB compression point is more than+11 dBm． The core area of the chip is 0. 86 mm×0. 39 mm．
12311 针对传统电磁继电器在起动机启动时保护能力弱、灵敏度低、寿命短、体积大等缺点，基于 0. 35 μm CMOS 工艺，设计了一种分时电压采样与保护的电子继电器控制集成电路。 An electronic relay control integrated circuit with time-sharing voltage sampling and protection was designed based on 0. 35 μm CMOS technology to overcome the disadvantages of the traditional electromagnetic relay in starting the starter，such as weaker protection ability，lower sensitivity，shorterlife-time，larger volume and so on．
12312 该电路通过 A/D 采样模块采集功率 MOSFET 的漏源电压和过流阈值电压，并利用减法器进行比较，用于判断起动机是否发生堵转，进而控制功率 MOSFET 的导通/截止，进一步判断起动机的开启或关断。 In this circuit，the drain-source voltage and the overcurrent thresholdvoltage of power MOSFETs were sampled by the A / D sampling module，and a subtractor was adopted tocompare the two voltages，which was used to judge whether the starter was blocked or not，and then tocontrol the ON/OFF of the power MOSFET，furthermore，to judge the opening or turning off of the starter．
12313 测试结果表明，该电子继电器可在 400 A 电流下正常启动和在 500 A 大电流下堵转330 ms后完成过流保护功能。 The test results show that the electronic relay can start normally at the current of 400 A and the overcurrentprotected function is completed after blocking 330 ms at the high currentof 500 A．